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Mono Color

• 8a0216bd9f - libs/ezsat/ezminisat.cc: use POSIX.2001 sigaction() instead on non-portable signal(). Siesh1oo 2014-03-10 15:02:58 +0100
• 0fb044a58f - Makefile, kernel/posix_compatibility.h/.cc: provide POSIX.2008 fake implementation of open_memstream()/fmemopen() for pre-POSIX.2008 systems. - Makefile: OSX build rules (Apple's gcc and clang have no -rdynamic option and no librt). - Makefile: Generate debugger symbols and don't optimize for size in debug target (otherwise the debugger pretty hard to use). - Makefile: Reorder target concatenation in order to avoid use-before-built problems for source-include and linker dependencies. - Makefile: On OSX/macports, qmake-qt4 is named 'qmake' (the default Qt4 installation name, unless the distribution changes it). - Makefile: For OSX/Macports, we need to pass -I/opt/local/include and -L/opt/local/lib to give GNU libraries precedence over Apple's. - Makefile: Build a local minisat copy just like abc (to avoid dependency on broken/unmaintained distribution header files). - .gitignore: Ignore minisat directory. Siesh1oo 2014-03-10 14:38:01 +0100
• 9327d434d5 - README: fix typo in sed-command for minisat-include fix. Siesh1oo 2014-03-10 14:37:14 +0100
• f6579282d7 - frontends/vhdl2verilog/vhdl2verilog.cc: #include <cerrno> for errno; use POSIX getcwd() for portability. Siesh1oo 2014-03-10 14:36:27 +0100
• c056217e72 - kernel/register.cc: need to #include <cerrno> or errno.h for errno. Siesh1oo 2014-03-10 14:36:23 +0100
• 6698d67d24 - kernel/driver.cc: need to #include <cerrno> or errno.h for errno. Siesh1oo 2014-03-10 14:36:12 +0100
• 8111938e96 - kernel/log.h: add rusage()-based fallback for systems without clock_gettime(). Siesh1oo 2014-03-10 14:36:07 +0100
• 40e0b79495 - libs/ezsat/ezsat.cc: need to #include <cmath> or math.h for math functions. Siesh1oo 2014-03-10 14:35:59 +0100
• f7c2cf6fe2 - passes/abc/abc.cc: #include <cerrno> for errno; use POSIX getcwd() for portability (get_current_dir_name() does not exist on BSD). Siesh1oo 2014-03-10 14:35:53 +0100
• 9b3d83359c - passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, passes/cmds/select.cc: #include <cerrno> for errno, use c++-style includes. Siesh1oo 2014-03-10 14:35:46 +0100
• 78c64a6401 Fixed a typo in RTLIL::Module::addReduce... Clifford Wolf 2014-03-10 12:07:26 +0100
• 5a15539c9b Improved verific command (added support for some operators) Clifford Wolf 2014-03-10 12:06:57 +0100
• c71791a1ff Improvements in verific command Clifford Wolf 2014-03-10 03:03:08 +0100
• fdef064b1d Added RTLIL::Module::add... helper methods Clifford Wolf 2014-03-10 03:02:27 +0100
• 8d06f9f2fe Added "verific" command Clifford Wolf 2014-03-09 20:40:04 +0100
• fcae92868d Fixed dumping of timing() { .. } block in libparse Clifford Wolf 2014-03-09 15:16:07 +0100
• 22aabe05c9 Verbose reading of liberty and constr files in ABC pass Clifford Wolf 2014-03-09 15:15:38 +0100
• e3b11ea2d6 Fixed bug in freduce command Clifford Wolf 2014-03-07 18:44:23 +0100
• 6f8865d81a Some minor code cleanups in freduce command Clifford Wolf 2014-03-07 18:29:04 +0100
• 620d51d9f7 Bugfix in ilang frontend autoidx recovery Clifford Wolf 2014-03-07 17:19:14 +0100
• f7bd0a5232 Use log_abort() and log_assert() in BTOR backend Clifford Wolf 2014-03-07 15:56:10 +0100
• 54d74cf616 Added freduce -dump Clifford Wolf 2014-03-06 22:06:58 +0100
• da5859a674 Added freduce -stop Clifford Wolf 2014-03-06 18:14:26 +0100
• 4d07f88258 Fixed gcc compiler warning Clifford Wolf 2014-03-06 16:37:19 +0100
• 9b9c3327cc Fixed undef handling in opt_reduce Clifford Wolf 2014-03-06 14:18:34 +0100
• 973507d85b Fixes for improved techmap of shifts with large B inputs Clifford Wolf 2014-03-06 13:22:10 +0100
• 97710ffad5 Fixed use of frozen literals in SatGen Clifford Wolf 2014-03-06 13:08:44 +0100
• 8406e7f7b6 Strictly zero-extend unsigned A-inputs of shift operations in techmap Clifford Wolf 2014-03-06 12:15:44 +0100
• 1ecaf1bb76 Added techmap -max_iter option Clifford Wolf 2014-03-06 12:15:17 +0100
• d7f29bb23f Improved techmap of shift with wide B inputs Clifford Wolf 2014-03-06 11:54:22 +0100
• a1bfde8c5e Strictly zero-extend unsigned A-inputs of shift operations Clifford Wolf 2014-03-06 11:53:37 +0100
• b1b8fe3a56 Switched to EZMINISAT_SIMPSOLVER as default SAT solver Clifford Wolf 2014-03-05 19:57:10 +0100
• 09805ee9ec Include id2ast pointers when dumping AST Clifford Wolf 2014-03-05 19:56:31 +0100
• d6a01fe412 Fixed merging of compatible wire decls in AST frontend Clifford Wolf 2014-03-05 19:55:58 +0100
• de7bd12004 Bugfix in recursive AST simplification Clifford Wolf 2014-03-05 19:45:33 +0100
• 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() Clifford Wolf 2014-03-03 02:14:27 +0100
• d5bd93997c ezSAT: Added frozen_literal() API Clifford Wolf 2014-03-03 02:13:17 +0100
• 895e9fc70c ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions Clifford Wolf 2014-03-03 02:12:45 +0100
• d500bd749f Added ezSAT::eliminated API to help the SAT solver remember eliminated variables Clifford Wolf 2014-03-01 21:00:34 +0100
• 23f0a12c72 ezSAT bugfix: don't call virtual methods in base class constructor Clifford Wolf 2014-03-01 20:59:00 +0100
• edc2146056 Removed ezSAT::assumed() API Clifford Wolf 2014-03-01 20:55:06 +0100
• e3debea4e6 Removed ezSAT built-in brute-froce solver Clifford Wolf 2014-03-01 20:53:09 +0100
• ef90236a5d Fixed vhdl2verilog temp dir name Clifford Wolf 2014-03-01 17:48:15 +0100
• 04999f4af0 Fixed vhdl2verilog help message Clifford Wolf 2014-03-01 17:47:19 +0100
• 9e99984336 Fixed const folding of $bu0 cells Clifford Wolf 2014-02-27 04:09:32 +0100
• ae5032af84 Fixed bit-extending in $mux argument (use $bu0 instead of $pos) Clifford Wolf 2014-02-26 21:32:19 +0100
• aaaa604853 Added support for $bu0 to SatGen Clifford Wolf 2014-02-26 21:31:34 +0100
• 6bc94b7eb2 Don't blow up constants unneccessarily in Verilog frontend Clifford Wolf 2014-02-24 12:41:25 +0100
• dab1612f81 Added support for Minisat::SimpSolver + ezSAT frezze() API Clifford Wolf 2014-02-23 01:35:59 +0100
• b76528d8a5 Fixed small memory leak in Pass::call() Clifford Wolf 2014-02-23 01:28:29 +0100
• f8c9143b2b Fixed bug in generation of undefs for $memwr MUXes Clifford Wolf 2014-02-22 17:08:00 +0100
• 548519875b Fixed bug (typo) in passes/opt/opt_const.cc Clifford Wolf 2014-02-22 17:07:22 +0100
• 337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) Clifford Wolf 2014-02-22 14:25:32 +0100
• 357f3f6e93 Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option Clifford Wolf 2014-02-22 11:34:31 +0100
• 1ec01d8c63 Made MiniSat solver backend configurable in ezminisat.h Clifford Wolf 2014-02-22 01:29:02 +0100
• 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst Clifford Wolf 2014-02-21 23:34:45 +0100
• 0a60f95224 Added vhdl2verilog Clifford Wolf 2014-02-21 18:59:49 +0100
• 79edcd4318 Progress in presentation Clifford Wolf 2014-02-21 14:59:59 +0100
• 038eac7414 Better handling of nameDef and nameRef in edif backend Clifford Wolf 2014-02-21 13:40:43 +0100
• f3ff29d410 Fixed instantiating multi-bit ports in edif backend Clifford Wolf 2014-02-21 13:10:36 +0100
• 3c5e973092 Use private namespace in mem_simple_4x1_map Clifford Wolf 2014-02-21 12:14:38 +0100
• 81b3f52519 Added tests/techmap/mem_simple_4x1 Clifford Wolf 2014-02-21 12:06:40 +0100
• 79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param Clifford Wolf 2014-02-21 10:40:15 +0100
• 2aff7b2a47 Progress in presentation Clifford Wolf 2014-02-21 02:13:02 +0100
• 9351e4d3ca Progress in presentation Clifford Wolf 2014-02-20 23:44:28 +0100
• 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap Clifford Wolf 2014-02-20 23:42:07 +0100
• 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." Clifford Wolf 2014-02-20 23:31:13 +0100
• 236fc4209c Added "extract -map %<design_name>" Clifford Wolf 2014-02-20 23:30:15 +0100
• 483c99fe46 Added "design -push" and "design -pop" Clifford Wolf 2014-02-20 23:28:59 +0100
• b0e84802ec Progress in presentation Clifford Wolf 2014-02-20 20:44:41 +0100
• 0dadfed46d Added connwrappers command Clifford Wolf 2014-02-20 20:44:11 +0100
• 4bd25edcd4 Cleanups in handling of read_verilog -defer and -icells Clifford Wolf 2014-02-20 19:12:32 +0100
• 98940260e1 Progress in presentation Clifford Wolf 2014-02-20 12:46:29 +0100
• 772330608a Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...) Clifford Wolf 2014-02-19 12:40:49 +0100
• 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-18 20:05:53 +0100
• 3d9da919d8 Progress in presentation Clifford Wolf 2014-02-18 19:37:39 +0100
• a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ Clifford Wolf 2014-02-18 19:23:32 +0100
• a78bba1f5c Added "sat -dump_cnf" Clifford Wolf 2014-02-18 09:29:08 +0100
• 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() Clifford Wolf 2014-02-18 09:28:05 +0100
• 61a2bf57b4 Improved non-verbose ezSAT::printDIMACS() format Clifford Wolf 2014-02-18 09:25:41 +0100
• 13051e6acf Added "sat -initsteps" Clifford Wolf 2014-02-18 09:03:16 +0100
• 02e6f2c5be Added Verilog support for "`default_nettype none" Clifford Wolf 2014-02-17 14:28:52 +0100
• 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups Clifford Wolf 2014-02-17 13:57:14 +0100
• 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver Andrew Zonenberg 2014-02-17 06:06:04 -0500
• 0fbc1a59dd Progress in presentation Clifford Wolf 2014-02-17 09:45:04 +0100
• ca53ef5098 Better preserve wires when flattening (in comparison to techmap) Clifford Wolf 2014-02-17 09:44:39 +0100
• 37cbb1ca60 Progress in presentation Clifford Wolf 2014-02-16 22:31:53 +0100
• 6d63f39eb6 Added some additional checks to techmap Clifford Wolf 2014-02-16 22:18:06 +0100
• a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap Clifford Wolf 2014-02-16 21:58:59 +0100
• 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean Clifford Wolf 2014-02-16 21:58:27 +0100
• 7d7e068dd1 Added a warning note about error reporting to read_verilog help message Clifford Wolf 2014-02-16 20:20:25 +0100
• f08c71b96c Progress in presentation Clifford Wolf 2014-02-16 17:56:19 +0100
• 42ce3db983 Fixed use of selection in splitnets command Clifford Wolf 2014-02-16 17:39:50 +0100
• d3dc22a90f Added recursion support to techmap Clifford Wolf 2014-02-16 17:16:44 +0100
• aeb36b0b8b Progress in presentation Clifford Wolf 2014-02-16 14:32:56 +0100
• 9c29969bbc Progress in presentation Clifford Wolf 2014-02-16 13:45:47 +0100
• 7ac524e8e8 Improved support for constant functions Clifford Wolf 2014-02-16 13:16:38 +0100
• b0ae19fa92 Now we are in Yoys 0.2.0+ development Clifford Wolf 2014-02-16 00:54:41 +0100
• c05c3098f1 Tagging Yoys 0.2.0 yosys-0.2.0 Clifford Wolf 2014-02-16 00:35:53 +0100
• 9a816b65a8 Added != support for relational select pattern Clifford Wolf 2014-02-16 00:16:54 +0100