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yosys-0.4

yosys-0.40

yosys-0.41

yosys-0.42

yosys-0.43

yosys-0.44

yosys-0.5

yosys-0.6

yosys-0.7

yosys-0.8

yosys-0.9

Mono Color

• 1c288adcc0 Some "const" cleanups in SigMap Clifford Wolf 2014-07-19 15:32:39 +0200
• 26f982ac0b Fixed bug in memory_share feedback-to-en code Clifford Wolf 2014-07-19 15:32:14 +0200
• e441f07d89 Added translation from read-feedback to en-signals in memory_share Clifford Wolf 2014-07-18 16:46:40 +0200
• 44f13aff92 Improved seeding of color rng in show command Clifford Wolf 2014-07-18 16:44:45 +0200
• a341931972 Only create collision detect logic in memory_share if necessary Clifford Wolf 2014-07-18 14:32:40 +0200
• ddb01df42e Bugfix in tests/memories/run-test.sh Clifford Wolf 2014-07-18 13:45:25 +0200
• 5d9127418b added tests/memories Clifford Wolf 2014-07-18 13:25:19 +0200
• ab4b26679f Added memory_share Clifford Wolf 2014-07-18 12:40:01 +0200
• a721f7d768 Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> Clifford Wolf 2014-07-18 11:36:34 +0200
• 309ae98246 Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port Clifford Wolf 2014-07-18 10:28:45 +0200
• 2d69c309f9 Added function-like cell creation helpers Clifford Wolf 2014-07-18 10:27:06 +0200
• a8cedb2257 Added log_id() helper function Clifford Wolf 2014-07-18 10:26:01 +0200
• ec3a798194 Also simulate unmapped memories in "make test" Clifford Wolf 2014-07-17 16:53:52 +0200
• 9b183539af Implemented dynamic bit-/part-select for memory writes Clifford Wolf 2014-07-17 16:49:23 +0200
• f1ca93a0a3 Fixed simlib.v model for $mem Clifford Wolf 2014-07-17 16:48:36 +0200
• 5867f6bcdc Added support for bit/part select to mem2reg rewriter Clifford Wolf 2014-07-17 13:49:32 +0200
• 6d69d4aaa8 Added support for constant bit- or part-select for memory writes Clifford Wolf 2014-07-17 13:13:21 +0200
• 1b00861d0a Improved opt_reduce handling of mem wr_en mux bits Clifford Wolf 2014-07-17 12:12:04 +0200
• 274c514879 Fixed RTLIL::SigSpec::append_bit() for appending constants Clifford Wolf 2014-07-17 12:10:57 +0200
• b76bf05cda Added support for "blackbox" attribute to iopadmap Clifford Wolf 2014-07-17 08:59:07 +0200
• 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap Clifford Wolf 2014-07-17 08:58:51 +0200
• b171a4c1bc Added "inout" ports support to read_liberty Clifford Wolf 2014-07-16 18:12:46 +0200
• 5057935722 Set blackbox attribute in "read_liberty -lib" Clifford Wolf 2014-07-16 18:12:16 +0200
• 24f58e57f3 Fixed spelling of "direction" in read_liberty messages Clifford Wolf 2014-07-16 18:02:28 +0200
• 02346cd1d5 Merged new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 14:15:33 +0200
• 73a345294a Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 13:46:27 +0200
• d678b6533d improved opt_reduce for $mem/$memwr WR_EN multiplexers Clifford Wolf 2014-07-16 13:37:41 +0200
• 543551b80a changes in verilog frontend for new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 12:23:47 +0200
• 765f172211 Changes to "memory" pass for new $memwr/$mem WR_EN interface Clifford Wolf 2014-07-16 12:13:13 +0200
• dcdd5c11b4 Updated simlib to new $mem/$memwr interface Clifford Wolf 2014-07-16 11:46:40 +0200
• 73e0e13d2f Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal Clifford Wolf 2014-07-16 11:38:02 +0200
• 964a67ac41 Added note to "make test": use git checkout of iverilog Clifford Wolf 2014-07-16 10:03:07 +0200
• 0f9ca49dc6 Added passing of various options to vhdl2verilog Clifford Wolf 2014-07-12 10:02:39 +0200
• 847e2ee4a1 Use "verilog -sv" to parse .sv files Clifford Wolf 2014-07-11 13:10:51 +0200
• 55a1b8dbac Fixed processing of initial values for block-local variables Clifford Wolf 2014-07-11 13:05:53 +0200
• 3b52121d32 now ignore init attributes on non-register wires in sat command Clifford Wolf 2014-07-05 11:17:40 +0200
• ee8ad72fd9 fixed parsing of constant with comment between size and value Clifford Wolf 2014-07-02 06:27:04 +0200
• 1c81ab49e7 small changes in presentation Clifford Wolf 2014-07-02 06:16:31 +0200
• d26561cc44 Tiny fix in presentation Clifford Wolf 2014-06-29 09:27:03 +0200
• 3a3f5d5923 Progress in presentation Clifford Wolf 2014-06-29 09:14:49 +0200
• 89c85cac41 Added links to some liberty files to README Clifford Wolf 2014-06-28 12:11:42 +0200
• 3e96ce8680 Progress in presentation Clifford Wolf 2014-06-26 22:05:39 +0200
• 076182c34e Fixed handling of mixed real/int ternary expressions Clifford Wolf 2014-06-25 10:05:36 +0200
• 4fc43d1932 More found_real-related fixes to AstNode::detectSignWidthWorker Clifford Wolf 2014-06-24 15:08:48 +0200
• a7aea17959 Progress in presentation Clifford Wolf 2014-06-22 12:50:29 +0200
• 3345fa0bab Little steps in realmath test bench Clifford Wolf 2014-06-21 21:43:04 +0200
• 65b2e9c064 fixed signdness detection for expressions with reals Clifford Wolf 2014-06-21 21:41:13 +0200
• 072604f30f fixed typo Clifford Wolf 2014-06-21 21:13:18 +0200
• b18fa95d2f Progress in presentation Clifford Wolf 2014-06-21 16:33:33 +0200
• 1c85584fe5 Do not create $dffsr cells with no-op resets in proc_dff Clifford Wolf 2014-06-19 12:29:29 +0200
• df76da8fd7 Added test case for AstNode::MEM2REG_FL_CMPLX_LHS Clifford Wolf 2014-06-17 21:49:59 +0200
• 80e4594695 Added AstNode::MEM2REG_FL_CMPLX_LHS Clifford Wolf 2014-06-17 21:39:25 +0200
• 798ff88855 Improved handling of relational op of real values Clifford Wolf 2014-06-17 12:47:51 +0200
• 88470283c9 Little steps in realmath test bench Clifford Wolf 2014-06-16 15:21:08 +0200
• 6c17d4f242 Improved ternary support for real values Clifford Wolf 2014-06-16 15:12:24 +0200
• 82bbd2f077 Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012 Clifford Wolf 2014-06-16 15:05:37 +0200
• 0c4c79c4c6 Fixed parsing of TOK_INTEGER (implies TOK_SIGNED) Clifford Wolf 2014-06-16 15:02:40 +0200
• 5bfe865cec Added found_real feature to AstNode::detectSignWidth Clifford Wolf 2014-06-16 15:00:57 +0200
• b1b96d199f Added more calls to "hierarchy" to README file Clifford Wolf 2014-06-15 11:51:51 +0200
• 398482eced Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath) Clifford Wolf 2014-06-15 09:39:22 +0200
• a4ec19c25c Added tests/realmath to "make test" Clifford Wolf 2014-06-15 09:31:03 +0200
• 4d1df128fa Improved AstNode::realAsConst for large numbers Clifford Wolf 2014-06-15 09:27:09 +0200
• 656685fa31 Improved realmath test bench Clifford Wolf 2014-06-15 08:48:41 +0200
• 7f57bc8385 Improved parsing of large integer constants Clifford Wolf 2014-06-15 08:48:17 +0200
• 48dc6ab98d Improved AstNode::asReal for large integers Clifford Wolf 2014-06-15 08:38:31 +0200
• 11d2add1b9 improved realmath test bench Clifford Wolf 2014-06-14 20:38:40 +0200
• 149fe83a8d improved (fixed) conversion of real values to bit vectors Clifford Wolf 2014-06-14 20:38:05 +0200
• 39eb347c67 progress in realmath test bench Clifford Wolf 2014-06-14 19:56:22 +0200
• d5765b5e14 Fixed relational operators for const real expressions Clifford Wolf 2014-06-14 19:33:58 +0200
• ebe2d73330 added first draft of real math testcase generator Clifford Wolf 2014-06-14 19:24:01 +0200
• 1a487303a0 Progress in presentation Clifford Wolf 2014-06-14 16:42:30 +0200
• 22a998903b Added %D and %c select commands Clifford Wolf 2014-06-14 16:19:32 +0200
• f3b4a9dd24 Added support for math functions Clifford Wolf 2014-06-14 13:36:23 +0200
• 406f86a91e Added realexpr.v test case Clifford Wolf 2014-06-14 12:01:17 +0200
• 9bd7d5c468 Added handling of real-valued parameters/localparams Clifford Wolf 2014-06-14 12:00:47 +0200
• fc7b6d172a Implemented more real arithmetic Clifford Wolf 2014-06-14 11:27:05 +0200
• 442a8e2875 Implemented basic real arithmetic Clifford Wolf 2014-06-14 08:51:22 +0200
• 9dd16fa41c Added real->int convertion in ast genrtlil Clifford Wolf 2014-06-14 07:44:19 +0200
• 7ef0da32cd Added Verilog lexer and parser support for real values Clifford Wolf 2014-06-13 11:29:23 +0200
• 482d9208aa Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch Clifford Wolf 2014-06-12 11:54:20 +0200
• 9a6cd64fc2 Now we are in Yoys 0.3.0+ development Clifford Wolf 2014-06-08 15:31:27 +0200
• ca125bf41b Tagging Yosys 0.3.0 yosys-0.3.0 Clifford Wolf 2014-06-08 15:28:36 +0200
• 94e9ee6bab Updated ABC to 7600ffb9340c Clifford Wolf 2014-06-08 10:12:39 +0200
• 3af7c69d1e added tests for new verilog features Clifford Wolf 2014-06-07 12:18:00 +0200
• 744e518467 fixed cell array handling of positional arguments Clifford Wolf 2014-06-07 12:17:06 +0200
• e275e8eef9 Add support for cell arrays Clifford Wolf 2014-06-07 11:48:50 +0200
• 0b1ce63a19 Added support for repeat stmt in const functions Clifford Wolf 2014-06-07 10:47:53 +0200
• 7c8a7b2131 further improved const function support Clifford Wolf 2014-06-07 00:02:05 +0200
• 5281562d0e made the generate..endgenrate keywords optional Clifford Wolf 2014-06-06 23:05:01 +0200
• 76da2fe172 improved const function support Clifford Wolf 2014-06-06 22:55:02 +0200
• 5c10d2ee36 fix functions with no block (but single statement, loop, etc.) Clifford Wolf 2014-06-06 21:29:23 +0200
• c82db39935 Added tests/simple/repwhile.v Clifford Wolf 2014-06-06 17:47:20 +0200
• ab54ce17c8 improved ast simplify of const functions Clifford Wolf 2014-06-06 17:40:45 +0200
• b5cd7a0179 added while and repeat support to verilog parser Clifford Wolf 2014-06-06 17:40:04 +0200
• f9c1cd5edb Improved error message for options after front-end filename arguments Clifford Wolf 2014-06-04 09:10:50 +0200
• abe6131d5a Merge 86f3e2402f into 7020f7fc13 Johann Glaser 2014-06-03 07:25:18 +0000
• 7020f7fc13 added tee cmd Clifford Wolf 2014-06-03 09:23:31 +0200
• 86f3e2402f new option for "stat" to write to a file Johann Glaser 2014-06-02 13:42:41 +0200
• 68c99bf734 Fixed log messages in memory_dff Clifford Wolf 2014-06-01 11:32:27 +0200
• d5497f770b Updated ABC to rev fa4404b395f0 Clifford Wolf 2014-05-29 11:03:15 +0200