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yosys-0.42

yosys-0.43

yosys-0.44

yosys-0.5

yosys-0.6

yosys-0.7

yosys-0.8

yosys-0.9

Mono Color

• 8ff71b5ae5 Added Frontend "+/" filename syntax for files from proc_share_dir Clifford Wolf 2014-08-15 02:08:02 +02:00
• d320e75087 document "techmap -map %<design-name>" Clifford Wolf 2014-08-15 02:00:53 +02:00
• c7afbd9d8e Fixed bug in "read_verilog -ignore_redef" Clifford Wolf 2014-08-15 01:53:22 +02:00
• 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() Clifford Wolf 2014-08-14 23:14:47 +02:00
• c83b990458 Changed the AST genWidthRTLIL subst interface to use a std::map Clifford Wolf 2014-08-14 23:02:07 +02:00
• 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern Clifford Wolf 2014-08-14 22:32:18 +02:00
• 6d56172c0d Fixed line numbers when using here-doc macros Clifford Wolf 2014-08-14 22:26:30 +02:00
• 85e3cc12ac Fixed handling of task outputs Clifford Wolf 2014-08-14 22:26:10 +02:00
• 5602cbde9f Simplified $__arraymul techmap rule Clifford Wolf 2014-08-14 20:53:21 +02:00
• 1bf7a18fec Added module->ports Clifford Wolf 2014-08-14 16:13:42 +02:00
• 746aac540b Refactoring of CellType class Clifford Wolf 2014-08-14 15:46:51 +02:00
• 13f2f36884 RIP $safe_pmux Clifford Wolf 2014-08-14 11:39:46 +02:00
• 28cf48e31f Some improvements in FSM mapping and recoding Clifford Wolf 2014-08-14 11:22:45 +02:00
• 996c06f64d Added "abc -D" for setting delay target Clifford Wolf 2014-08-14 11:05:25 +02:00
• a878095b46 Updated ABC to 4935c2b946de Clifford Wolf 2014-08-14 10:19:12 +02:00
• 7e758d5fbb Added techmap support for actual lookahead carry unit Clifford Wolf 2014-08-13 18:40:57 +02:00
• 9a065509ac Preparations for lookahead ALU support in techmap.v Clifford Wolf 2014-08-13 16:36:30 +02:00
• 28bc7aeb93 Filter ANSI escape sequences from ABC output Clifford Wolf 2014-08-13 13:40:29 +02:00
• c27120fcbc New interface for $__alu in techmap.v Clifford Wolf 2014-08-13 13:04:28 +02:00
• f53984795d Added support for non-standard """ macro bodies Clifford Wolf 2014-08-13 13:03:38 +02:00
• 9d353fc543 Fixed handling of constant-true branches in proc_clean Clifford Wolf 2014-08-12 17:35:22 +02:00
• 1dd8252169 Added test_verific mode to tests/fsm/generate.py Clifford Wolf 2014-08-12 15:43:30 +02:00
• e5ac8fdf2b Fixed SigBit(RTLIL::Wire *wire) constructor Clifford Wolf 2014-08-12 15:39:48 +02:00
• 593264e9ed Fixed building verific bindings Clifford Wolf 2014-08-12 15:21:06 +02:00
• cad98bcd89 Added multi-dim memory test (requires iverilog git head) Clifford Wolf 2014-08-12 10:37:47 +02:00
• 5215723c64 Another build fix by americanrouter (via reddit) Clifford Wolf 2014-08-11 15:55:41 +02:00
• 788bd02f97 Fixed FSM mapping for multiple reset-like signals Clifford Wolf 2014-08-10 12:04:02 +02:00
• 9d4362990f Fixed "share" for complex scenarios with never-active cells Clifford Wolf 2014-08-09 17:07:20 +02:00
• b9811d5aff Do not share any $reduce_* cells (its complicated and not worth it anyways) Clifford Wolf 2014-08-09 15:17:54 +02:00
• 2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states Clifford Wolf 2014-08-09 14:49:51 +02:00
• 51aa5544fb Improved FSM tests Clifford Wolf 2014-08-08 14:30:45 +02:00
• 58ac605470 Another fsm_extract bugfix Clifford Wolf 2014-08-08 14:55:11 +02:00
• 7067c43ec0 Fixed "fsm -export" Clifford Wolf 2014-08-08 14:49:06 +02:00
• cb6ca08a53 Fixed sharing of reduce operator Clifford Wolf 2014-08-08 14:24:09 +02:00
• 7c94024fc3 Fixed fsm_extract for wreduced muxes Clifford Wolf 2014-08-08 13:47:20 +02:00
• c07774b0b6 Added FSM test bench Clifford Wolf 2014-08-08 13:12:18 +02:00
• 622ebab671 Added "sat -prove-skip" Clifford Wolf 2014-08-08 13:11:54 +02:00
• 0b8b8d41eb Fixed build with gcc-4.6 Clifford Wolf 2014-08-07 22:37:01 +02:00
• c55eb8f8a6 Use "-keepdc" in "miter -equiv -flatten" Clifford Wolf 2014-08-07 16:42:35 +02:00
• 2dc3333734 Also allow "module foobar(input foo, output bar, ...);" syntax Clifford Wolf 2014-08-07 16:41:27 +02:00
• 312ee00c9e Added adff2dff.v (for techmap -share_map) Clifford Wolf 2014-08-07 16:14:38 +02:00
• d259abbda2 Added AST_MULTIRANGE (arrays with more than 1 dimension) Clifford Wolf 2014-08-06 15:43:46 +02:00
• b4f10e342c Various improvements in memory_dff pass Clifford Wolf 2014-08-06 14:31:38 +02:00
• 2501abe1ee Various fixes and improvements in wreduce pass Clifford Wolf 2014-08-05 19:01:41 +02:00
• 5b3dc07b9a Removed old "constmap" from wreduce code Clifford Wolf 2014-08-05 16:53:53 +02:00
• 523df73145 Added support for truncating of wires to wreduce pass Clifford Wolf 2014-08-05 14:47:03 +02:00
• d3b1a29708 Cleanups and improvements in wreduce pass Clifford Wolf 2014-08-05 13:11:04 +02:00
• 1c182cedb7 Added mux support to wreduce command Clifford Wolf 2014-08-05 12:49:53 +02:00
• 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend Clifford Wolf 2014-08-05 12:15:53 +02:00
• 0129d41efa Fixed AST handling of variables declared inside a functions main block Clifford Wolf 2014-08-05 08:35:51 +02:00
• 0bb6942218 Added "show -signed" Clifford Wolf 2014-08-04 15:33:51 +02:00
• b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax Clifford Wolf 2014-08-04 15:19:24 +02:00
• ebbbe7fc83 Added RTLIL::IdString::in(...) Clifford Wolf 2014-08-04 15:08:35 +02:00
• c7f99be3be Fixed "share" for memory read ports Clifford Wolf 2014-08-03 20:19:50 +02:00
• 358bf70a21 Added "wreduce" to some of the standard test benches Clifford Wolf 2014-08-03 20:03:16 +02:00
• 027376515a Progress in "wreduce" pass Clifford Wolf 2014-08-03 20:02:42 +02:00
• 0b02f6ca30 Added "wreduce" command (work in progress) Clifford Wolf 2014-08-03 15:02:05 +02:00
• 653edd7a2f Added query() API to ModIndex Clifford Wolf 2014-08-03 15:00:38 +02:00
• 75423169c5 Added ID() macro for static IdStrings Clifford Wolf 2014-08-03 14:59:13 +02:00
• 014a41fcf3 Implemented recursive techmap Clifford Wolf 2014-08-03 12:40:43 +02:00
• 9bb5298c10 Fixes in show command (related to new IdString) Clifford Wolf 2014-08-03 12:40:23 +02:00
• 08ec33a5e5 Implemented simplemap support for "techmap -extern" Clifford Wolf 2014-08-02 21:55:13 +02:00
• bc947d4c7b Fixed a va_list corruption in logv_error() Clifford Wolf 2014-08-02 21:54:30 +02:00
• 88cf00ce78 Be more conservative with printing decimal numbers in verilog backend Clifford Wolf 2014-08-02 21:54:02 +02:00
• ca1b5d50e0 Improved verilog output for ordinary $mux cells Clifford Wolf 2014-08-02 21:10:08 +02:00
• b6acbc82e6 Bugfix in "techmap -extern" Clifford Wolf 2014-08-02 20:54:30 +02:00
• 8e7361f128 Removed at() method from RTLIL::IdString Clifford Wolf 2014-08-02 19:08:02 +02:00
• 04727c7e0f No implicit conversion from IdString to anything else Clifford Wolf 2014-08-02 18:58:40 +02:00
• 768eb846c4 More bugfixes related to new RTLIL::IdString Clifford Wolf 2014-08-02 16:03:18 +02:00
• 08392aad8f Limit size of log_signal buffer to 100 elements Clifford Wolf 2014-08-02 15:52:21 +02:00
• e590ffc84d Improvements in new RTLIL::IdString implementation Clifford Wolf 2014-08-02 15:44:10 +02:00
• 8fd1c269ac Fixed a performance bug in opt_reduce Clifford Wolf 2014-08-02 15:12:16 +02:00
• 60f3dc9923 Implemented new reference counting RTLIL::IdString Clifford Wolf 2014-08-02 15:11:35 +02:00
• 97ad0623df Fixed memory corruption related to id2cstr() Clifford Wolf 2014-08-02 13:34:07 +02:00
• b9bd22b8c8 More cleanups related to RTLIL::IdString usage Clifford Wolf 2014-08-02 13:11:01 +02:00
• 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code Clifford Wolf 2014-08-02 00:45:25 +02:00
• 75ffd1643c Added logfile hash to statistics footer Clifford Wolf 2014-08-01 19:43:28 +02:00
• bd74ed7da4 Replaced sha1 implementation Clifford Wolf 2014-08-01 19:01:10 +02:00
• 1e224506be Added per-pass cpu usage statistics Clifford Wolf 2014-08-01 18:42:10 +02:00
• d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor Clifford Wolf 2014-08-01 16:53:15 +02:00
• 97a17d39e2 Packed SigBit::data and SigBit::offset in a union Clifford Wolf 2014-08-01 15:25:42 +02:00
• 5e641acc90 Consolidated hana test benches into fewer files Clifford Wolf 2014-08-01 03:57:37 +02:00
• 03ef9a75c6 Added "test_autotb -n <num_iter>" option Clifford Wolf 2014-08-01 03:55:51 +02:00
• 32a1cc3efd Renamed modwalker.h to modtools.h Clifford Wolf 2014-07-31 23:30:18 +02:00
• 62c8a71525 Various cleanups in Makefile, Renamed default configurations Clifford Wolf 2014-07-31 23:14:17 +02:00
• 069fe0db42 Added compiler + compiler version + compiler flags to version string Clifford Wolf 2014-07-31 23:07:00 +02:00
• c6fd82c70b Fixed build of verific bindings Clifford Wolf 2014-07-31 16:45:23 +02:00
• cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions Clifford Wolf 2014-07-31 16:38:54 +02:00
• b5a9e51b96 Added "trace" command Clifford Wolf 2014-07-31 15:02:16 +02:00
• cd9407404a Added RTLIL::Monitor Clifford Wolf 2014-07-31 14:34:12 +02:00
• e6d33513a5 Added module->design and cell->module, wire->module pointers Clifford Wolf 2014-07-31 14:11:39 +02:00
• 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace Clifford Wolf 2014-07-31 13:19:47 +02:00
• 1202f7aa4b Renamed "stdcells.v" to "techmap.v" Clifford Wolf 2014-07-31 02:32:00 +02:00
• 6ca0c569d9 Added "techmap -assert" Clifford Wolf 2014-07-31 02:21:41 +02:00
• 41555cde10 Reorganized stdcells.v (no actual code change, just moved and indented stuff) Clifford Wolf 2014-07-31 02:21:06 +02:00
• 6166c76831 Added "yosys -A" Clifford Wolf 2014-07-31 01:05:27 +02:00
• e5c245df9d Added "yosys -Q" Clifford Wolf 2014-07-31 00:53:21 +02:00
• 2541489105 Added techmap CONSTMAP feature Clifford Wolf 2014-07-30 22:04:30 +02:00
• 7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections Clifford Wolf 2014-07-30 20:18:48 +02:00
• 6400ae3648 Added write_file command Clifford Wolf 2014-07-30 19:59:29 +02:00