Miodrag Milanovic
f691cf9df2
Use read_techlib where applicable in tests
2026-06-25 08:49:02 +02:00
Miodrag Milanovic
51403bb4bd
Use read_techlib where applicable
2026-06-25 08:49:02 +02:00
Miodrag Milanovic
219982941a
Create a full copy of read_verilog to read_techlib
2026-06-25 08:48:07 +02:00
Miodrag Milanović
23aadd92ab
Merge pull request #5985 from YosysHQ/logid_left
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Remove leftover use of log_id
2026-06-24 07:15:32 +00:00
Miodrag Milanovic
fd3ec58055
Remove leftover use of log_id
2026-06-24 08:04:48 +02:00
KrystalDelusion
a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown
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equiv_opt: Add ignore-unknown-cells
2026-06-23 19:58:30 +00:00
Miodrag Milanović
30d0b39a15
Merge pull request #5982 from YosysHQ/cleanup
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File cleanup
2026-06-23 14:07:10 +00:00
Miodrag Milanovic
43d8a84bdc
Add pre-commit config file
2026-06-23 07:30:54 +02:00
Miodrag Milanovic
55034dbe91
Remaining fix
2026-06-23 07:26:12 +02:00
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a
End of file fix
2026-06-23 07:23:41 +02:00
Miodrag Milanovic
3ac58b3ac1
Fixed line endings
2026-06-23 07:17:22 +02:00
Miodrag Milanovic
1f0ac8fffc
Remove utf-8 marker
2026-06-23 07:14:20 +02:00
Miodrag Milanovic
f362e1db0e
Remove executable flag from .v files
2026-06-23 07:12:43 +02:00
KrystalDelusion
fe8f29b5f8
Merge pull request #5975 from dobios/patch-1
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[docs] nit: least/most significant bits referred to using LSB/MSB instead of LSb/MSb
2026-06-22 23:21:34 +00:00
KrystalDelusion
e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing
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write_verilog: Fix upto indexing for single bit
2026-06-22 23:04:16 +00:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells
2026-06-23 10:54:00 +12:00
Miodrag Milanović
0bd04dbae3
Merge pull request #5980 from YosysHQ/synth_intel
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synth_intel: fix broken dsp mapping
2026-06-22 16:46:02 +00:00
Miodrag Milanovic
09eef69e31
synth_intel: fix broken dsp mapping
2026-06-22 17:51:26 +02:00
Miodrag Milanović
6edbcecc52
Merge pull request #5972 from YosysHQ/ci_mingw64
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Add mingw64 build to CI
2026-06-22 14:54:56 +00:00
Miodrag Milanović
9139c94c8c
Merge pull request #5977 from YosysHQ/bitwuzla
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smtbmc: support latest bitwuzla
2026-06-22 14:23:35 +00:00
Miodrag Milanovic
ed654de3d9
Add mingw64 build to CI
2026-06-22 16:22:13 +02:00
nella
57ec784983
Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements
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Add muxcover x peepopt regression test (#964 ).
2026-06-22 10:13:43 +00:00
nella
8f5d2d5894
Use -assert-none.
2026-06-22 11:12:00 +02:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index
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Optimize upto vector indexing (Fix #892 ).
2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
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Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
Miodrag Milanović
f699624abf
Merge pull request #5978 from YosysHQ/remove_def
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Remove define since snprintf is supported in MSVC now
2026-06-22 08:49:26 +00:00
Miodrag Milanovic
94e43f7675
Remove define since snprintf is supported in MSVC now
2026-06-22 09:50:39 +02:00
Miodrag Milanovic
ebcbc06951
smtbmc: support latest bitwuzla
2026-06-22 08:40:16 +02:00
Amelia Dobis
41566a6b70
more typo found
2026-06-19 17:47:39 -04:00
Amelia Dobis
54d43d85e3
[docs] nit: usign the right acronym to refer to the right thing
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Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
2026-06-19 17:30:28 -04:00
Krystine Sherwin
b77bb851ed
tests: Add mixed_upto write_verilog test
2026-06-19 11:20:01 +12:00
Krystine Sherwin
338d4adef2
write_verilog: Fix upto indexing for single bit
2026-06-19 10:18:27 +12:00
nella
5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402
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Fix: `read_verilog` doesn't respect `signed` keyword
2026-06-18 16:53:37 +00:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer
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proc_dlatch - infer $adlatch (Fix #5910 ).
2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745
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Fix `chparam` values are unsigned when using read_verilog frontend
2026-06-18 16:50:22 +00:00
Miodrag Milanović
c9805ceb33
Merge pull request #5966 from maliberty/lz4-1.10.0-cve
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Update lz4 to 1.10.0 for CVE-2014-4715, CVE-2021-3520, CVE-2019-17543
2026-06-18 11:32:12 +00:00
Matt Liberty
7fbeb344a4
Update lz4 to 1.10.0 for CVE-2014-4715, CVE-2021-3520, CVE-2019-17543
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Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
2026-06-18 07:00:59 +00:00
Miodrag Milanović
72f6df873a
Merge pull request #5964 from YosysHQ/mingw_fix
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Fix share lookup for mingw builds
2026-06-17 18:32:02 +00:00
Miodrag Milanovic
88d4af94cf
Fix share lookup for mingw builds
2026-06-17 10:40:13 +02:00
Miodrag Milanović
e2903c4a5c
Merge pull request #5959 from YosysHQ/improve_test
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Improve test
2026-06-16 08:46:11 +00:00
Miodrag Milanović
211fa48ce5
Merge pull request #5962 from YosysHQ/update_abc
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Update ABC as per 2026-06-15
2026-06-16 08:39:41 +00:00
Miodrag Milanovic
3af45e7d04
Some more explanations
2026-06-16 10:31:37 +02:00
Miodrag Milanovic
0584587f9a
Make compilation like by abc scripts
2026-06-16 10:07:45 +02:00
Miodrag Milanovic
83ee00d312
Update ABC as per 2026-06-15
2026-06-15 19:42:17 +02:00
Emil J
f33cc39a0c
Merge pull request #5958 from YosysHQ/emil/opt_muxtree-single-driver
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opt_muxtree: error on multiple drivers
2026-06-15 15:00:48 +00:00
nella
c0709b1b4e
Fixup issue test.
2026-06-15 16:23:44 +02:00
Miodrag Milanovic
782f9ddd24
Added functional tests option
2026-06-15 16:04:37 +02:00
nella
eb4703808a
Add tests.
2026-06-15 15:46:13 +02:00
nella
a5bdb29d7f
Recognise asynchronous set/reset.
2026-06-15 15:44:50 +02:00
