mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-17 04:35:44 +00:00
Code Activity
17752 commits 136 branches 69 tags 59 MiB
Commit graph

17752 commits

This branch
This branch
All branches
Author SHA1 Message Date
Stan Lee
f026cebaf6 address comments 2026-01-21 15:16:45 -08:00
Stan Lee
f14eb4a7bb only check reg cells 2026-01-21 15:13:55 -08:00
Stan Lee
269b70c0f9 compiles 2026-01-21 12:32:38 -08:00
Stan Lee
0018037c16 minor changes 2026-01-21 12:25:28 -08:00
Stan Lee
e824c8e0d6 ready for review 2026-01-21 09:00:46 -08:00
Stan Lee
31e32af4a8 greptile 2026-01-21 08:54:43 -08:00
Stan Lee
d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Stan Lee
29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee
45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee
60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee
a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee
0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee
80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Stan Lee
c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee
6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee
186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee
e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee
15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Stan Lee
4a1af73ec0 activity pass and a vcd writer bug fix 2026-01-16 16:32:04 -08:00
Akash Levy
a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J
71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log 
read_verilog: remove log I left behind by accident
 2026-01-13 17:48:30 +00:00
Emil J. Tywoniak
83c1364eeb read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
Emil J
8da113b7f0
Merge pull request #5502 from YosysHQ/emil/digit-separator 
Use digit separators for large decimal integers
 2026-01-13 17:42:24 +00:00
Emil J
d9956b20f8
Merge pull request #5603 from YosysHQ/emil/makefile-no-ast-header 
Makefile: no longer install ast.h and ast_binding.h
 2026-01-13 17:18:40 +00:00
Emil J
ff3c24fcdc
Merge pull request #5521 from YosysHQ/emil/merge-queues 
.github: trigger everything that triggers on main or PRs on merge queue
 2026-01-13 17:22:37 +01:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
Emil J. Tywoniak
8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Emil J. Tywoniak
21e6833010 Makefile: no longer install ast.h and ast_binding.h 2026-01-13 16:33:11 +01:00
Miodrag Milanović
8f00c1824f
Merge pull request #5602 from YosysHQ/year_update 
Update year in banner and license
 2026-01-13 15:30:42 +01:00
Miodrag Milanovic
0e6973037d Update year in banner and license 2026-01-13 14:23:51 +01:00
nella
b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Miodrag Milanović
77005b69a2
Merge pull request #5601 from YosysHQ/release/v0.61 
Release version 0.61
 2026-01-13 09:39:50 +01:00
Miodrag Milanovic
b08e044994 Next dev cycle 2026-01-13 09:24:49 +01:00
Miodrag Milanovic
5ae48ee25f Release version 0.61 2026-01-13 08:35:02 +01:00
Akash Levy
58192ad8a6
Merge branch 'YosysHQ:main' into main 2026-01-12 22:52:03 -08:00
Miodrag Milanović
51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
github-actions[bot]
78cbc21b94 Bump version 2026-01-13 00:22:49 +00:00
Emil J
cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic
b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović
72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J
f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic
2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan
37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
github-actions[bot]
991e704899 Bump version 2026-01-09 00:26:46 +00:00
KrystalDelusion
cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Emil J
c7b839ef5a
Merge pull request #5530 from rocallahan/parallel-opt-merge 
Parallelize `opt_merge`
 2026-01-08 10:43:44 +01:00
Robert O'Callahan
8da919587d Parallelize opt_merge. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Akash Levy
e332ba807d
Merge branch 'YosysHQ:main' into main 2026-01-07 12:40:39 -08:00
github-actions[bot]
35321cd292 Bump version 2026-01-07 00:25:36 +00:00
Krystine Sherwin
9a09758f56
Test empty switches 2026-01-07 13:21:33 +13:00