Emil J. Tywoniak
44b0fdc2bf
bbox_derive: add assert and debug print
2024-05-03 20:43:01 +02:00
Emil J. Tywoniak
e8c58a5528
bbox_derive: fix unininitialized memory UB when run with no named args
2024-05-03 20:41:42 +02:00
Martin Povišer
4c000d3aba
Add new bbox_derive command for blackbox derivation
2024-05-03 20:39:11 +02:00
Emil J. Tywoniak
e939182e68
cellmatch: add comments
2024-05-03 16:42:41 +02:00
Martin Povišer
b143e5678f
cellmatch: Rename the special design to $cellmatch
2024-05-03 16:42:41 +02:00
Martin Povišer
c0e68dcc4d
cellmatch: Add debug print
2024-05-03 16:42:41 +02:00
Martin Povišer
6a9858cdad
cellmatch: Delegate evaluation to ConstEval
2024-05-03 16:42:41 +02:00
Martin Povišer
86e1080f05
cellmatch: New pass
2024-05-03 16:42:41 +02:00
Martin Povišer
6ff4ecb2b4
techmap: Remove techmap_chtype from the result
2024-05-03 13:33:28 +02:00
Martin Povišer
fc82251105
techmap: Support dynamic cell types
2024-05-03 13:33:28 +02:00
N. Engelhardt
34d9a7451e
Merge pull request #4333 from YosysHQ/fix_hierarchy_generate
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fix hierarchy -generate mode handling of cells
2024-04-25 09:56:24 +02:00
KrystalDelusion
c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup
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Typo fixing
2024-04-25 09:54:48 +12:00
Martin Povišer
171577f909
Merge pull request #4340 from gadfort/abc-lib-merge
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add support for using ABCs library merging when providing multiple liberty files
2024-04-17 22:01:20 +02:00
Jannis Harder
2bd889a59a
formalff -setundef: Fix handling for has_srst FFs
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The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.
This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
Martin Povišer
b827b9862f
Merge pull request #4265 from povik/iattr_help
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memory_map: Explain `-iattr` better
2024-04-13 18:13:58 +02:00
Martin Povišer
4a8cdfabbb
Merge pull request #4169 from povik/clean-opt_clean-step2
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opt_clean: Remove dead assertion
2024-04-13 18:12:40 +02:00
Peter Gadfort
a48825a604
add support for using ABCs library merging when providing multiple liberty files
2024-04-12 13:57:29 -04:00
N. Engelhardt
b87327d1b9
fix hierarchy -generate mode handling of cells
2024-04-12 13:38:33 +02:00
Emil J
c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning
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opt_demorgan: fix extra args warning
2024-04-10 12:49:14 +02:00
Martin Povišer
b00abe4a26
Extend log command with -push, -pop, -header options
2024-04-10 11:49:20 +02:00
Martin Povišer
47931f9050
Merge pull request #4295 from gadfort/add-ports-stat
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add port statistics to stat command
2024-04-08 11:12:02 +02:00
Emil J. Tywoniak
4bb3b099d2
opt_demorgan: fix extra args warning
2024-04-03 10:02:53 +02:00
N. Engelhardt
c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
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Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Peter Gadfort
160e3e089a
add port statistics to stat command
2024-03-22 09:20:20 -04:00
Krystine Sherwin
3eeefd23e3
Typo fixup(s)
2024-03-18 11:09:23 +13:00
N. Engelhardt
e4f11eb0a0
Merge pull request #4228 from povik/synth-inject
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synth: Introduce `-extra-map` for amending techmap
2024-03-11 14:55:45 +01:00
Martin Povišer
206d894c56
check: Omit private wires in loop report
2024-03-11 10:45:36 +01:00
Martin Povišer
d01728aaa5
celledges: Register async FF paths
2024-03-11 10:45:36 +01:00
Martin Povišer
4fdcf388d3
check: Assert edges data is not out-of-bounds
2024-03-11 10:45:17 +01:00
Martin Povišer
b6112b3551
check: Consider read ports in loop detection
2024-03-11 10:45:17 +01:00
Martin Povišer
fa74d0bd1a
check: Use cell edges data in detecting combinational loops
2024-03-11 10:43:49 +01:00
Martin Povišer
c5ae74af34
check: Improve found loop logging
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Print the detected loop in-order, and include source location for each
node, if available.
2024-03-11 10:43:49 +01:00
N. Engelhardt
d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
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celledges: support shift ops
2024-03-08 09:35:47 +01:00
Martin Povišer
158fbf881e
memory_map: Explain -iattr better
2024-03-06 15:15:37 +01:00
Jannis Harder
04ecabdd1f
Merge pull request #4222 from jix/pdr-X
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write_aiger: Include `$assert` and `$assume` cells in -ywmap output
2024-03-05 15:13:51 +01:00
Jannis Harder
d8cdc213a6
rename -witness: Bug fix and rename formal cells
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Rename formal cells in addition to witness signals. This is required to
reliably track individual property states for the non-smtbmc flows.
Also removes a misplced `break` which resulted in only partial witness
renaming.
2024-03-04 16:53:03 +01:00
Jannis Harder
16f6386613
Merge pull request #4224 from povik/equiv_simple-fix
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equiv_simple: Take FFs into account for driver map
2024-03-04 15:53:34 +01:00
N. Engelhardt
6dc5da3ed9
Merge pull request #4232 from povik/mem-ui-fixes
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opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-26 16:09:27 +01:00
Roland Coeurjoly
4a2fb18718
Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc
2024-02-25 17:23:56 +01:00
Roland Coeurjoly
033fa10307
We use CXX instead of LD for linking yosys-filterlib
2024-02-25 16:49:28 +01:00
Martin Povišer
030d639201
opt_mem, memory_*: Refuse to operate in presence of processes
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Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
2024-02-23 12:27:53 +01:00
Martin Povišer
975517b022
memory_memx: Fix log header
2024-02-23 12:27:10 +01:00
Martin Povišer
53ca7b48f8
techmap: Fix help message wording
2024-02-22 22:00:56 +01:00
Martin Povišer
4c96546717
equiv_simple: Take FFs into account for driver map
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This fixes an issue introduced in commit 26644ea
2024-02-21 12:05:52 +01:00
Austin Rovinski
03cadf6474
dfflibmap: use patmatch() from kernel/yosys.cc
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Replace OS matching functions with yosys kernel function
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-20 11:04:55 -05:00
Miodrag Milanović
bc8a3a5b18
Merge pull request #4219 from rovinski/master
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dfflibmap: Add a -dont_use flag to ignore cells
2024-02-20 12:43:44 +01:00
Miodrag Milanović
a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href
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show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-19 20:50:53 +01:00
Austin Rovinski
5059bb1d4f
dfflibmap: force PathMatchSpecA on WIN32
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Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 14:40:46 -05:00
Austin Rovinski
689feed012
dfflibmap: Add a -dont_use flag to ignore cells
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This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 13:00:18 -05:00
Martin Povišer
db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
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proc_rom: don't assert on big actionless switch.
2024-02-19 16:21:40 +01:00
