mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-19 19:02:04 +00:00
Code Activity
8073 commits 123 branches 56 tags 58 MiB
Commit graph

2 commits

Author SHA1 Message Date
Larry Doolittle
50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
dh73
cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Renamed from techlibs/altera_intel/max10/cells_map_max10.v (Browse further)