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Code Activity
14627 commits 93 branches 53 tags 44 MiB
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Author SHA1 Message Date
Alain Dargelas
4132636712 Activity computation 2024-10-16 20:52:07 -07:00
Alain Dargelas
156bfafea0 update 2024-10-16 20:49:00 -07:00
Akash Levy
01dc929515 Bump yosys-slang dep 2024-10-16 20:46:46 -07:00
Alain Dargelas
3f7c392e1a activity computation 2024-10-16 20:41:26 -07:00
Akash Levy
0ba36ea83f Update yosys-slang dep 2024-10-16 20:00:55 -07:00
Akash Levy
e4ddfed7a2 Add UPF linking 2024-10-16 20:00:46 -07:00
Akash Levy
ae4fc61127
Merge branch 'YosysHQ:main' into main 2024-10-16 19:59:24 -07:00
github-actions[bot]
a54f632258 Bump version 2024-10-17 00:20:44 +00:00
Akash Levy
9de07e57b7 Add editor settings for vscode 2024-10-16 16:11:18 -07:00
Akash Levy
c8b6cf72e8 Bump dep 2024-10-16 14:27:52 -07:00
Akash Levy
711e1f3164
Merge branch 'YosysHQ:main' into main 2024-10-16 13:21:03 -07:00
KrystalDelusion
f137509505
Merge pull request #4332 from YosysHQ/krys/help_docs 
Add docs generation from cells help output
 2024-10-17 05:01:35 +13:00
Krystine Sherwin
e9d9e92804
Docs: Make code_examples/extensions parallel safe 2024-10-17 04:40:21 +13:00
Martin Povišer
9432e972f7
Merge pull request #4626 from povik/select-t-at 
select: Add new `t:@<name>` syntax
 2024-10-16 10:18:05 +02:00
Akash Levy
70c4a2f6a0
Merge branch 'YosysHQ:main' into main 2024-10-16 00:26:44 -07:00
Akash Levy
eeed79b3f2
Merge pull request #6 from alaindargelas/revert-5-power_resim 
Revert "auto name change until openSTA signal name parsing is fixed"
 2024-10-15 18:38:17 -07:00
alaindargelas
5019bd826d
Revert "auto name change until openSTA signal name parsing is fixed" 2024-10-15 18:36:37 -07:00
github-actions[bot]
11e94cc97c Bump version 2024-10-16 00:20:45 +00:00
Emil J. Tywoniak
f9f509bc25 select: add t:@<name> test 2024-10-15 21:06:06 +02:00
Akash Levy
b5d0d2b262 Bump yosys-slang 2024-10-15 06:45:56 -07:00
Akash Levy
cafd4cbbe8
Merge branch 'YosysHQ:main' into main 2024-10-15 06:43:06 -07:00
Emil J. Tywoniak
81bbde62ca verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00
Akash Levy
98db6bd2d8 muldiv_c peepopt pass 2024-10-15 05:29:00 -07:00
Akash Levy
8afa827b94 Bump yosys-slang dep 2024-10-15 03:23:24 -07:00
Martin Povišer
09be0351ce select: Add new t:@<name> syntax 2024-10-15 12:22:02 +02:00
Akash Levy
1be0a50185 Fix comma that pyosys hates 2024-10-15 03:20:54 -07:00
Akash Levy
ab05f03b70 Hacky pyosys workaround til Yosys fixes the issue 2024-10-15 03:20:15 -07:00
Akash Levy
b2b38ab81d
Merge branch 'YosysHQ:main' into main 2024-10-15 01:58:59 -07:00
Akash Levy
7be87935bd
Merge pull request #5 from alaindargelas/power_resim 
auto name change until openSTA signal name parsing is fixed
 2024-10-14 23:19:52 -07:00
Alain Dargelas
ecb9d3703b auto name change until openSTA signal name parsing is fixed 2024-10-14 21:14:45 -07:00
github-actions[bot]
adb6cdb167 Bump version 2024-10-15 00:20:48 +00:00
Krystine Sherwin
bc77575c22
Docs: Fix word_logic.rst 
It somehow got lost in the rebase.
 2024-10-15 11:46:21 +13:00
Krystine Sherwin
c93fd54e43
ci: Install docs/reqs (namely, furo-ys) 2024-10-15 11:37:52 +13:00
Krystine Sherwin
27b8b4e81e
Docs: Fix missing groups 
$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
 2024-10-15 11:08:30 +13:00
Krystine Sherwin
1513366f21
Docs: Adding mux cell descriptions 
Also making ver2 cell descriptions consistently spaced.
 2024-10-15 07:37:34 +13:00
Krystine Sherwin
dfe803b5c6
Docs: Comments from @jix 
- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor
 2024-10-15 07:37:20 +13:00
Krystine Sherwin
927dc445dd
Docs: Render cell titles 
Also put property lists *after* cell description.
 2024-10-15 07:35:42 +13:00
Krystine Sherwin
7216f07691
Docs: Define is_evaluable 2024-10-15 07:35:41 +13:00
Krystine Sherwin
9d808caba6
Docs: Add note on $check 2024-10-15 07:35:41 +13:00
Krystine Sherwin
e40134c856
Docs: Update for properties 
Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
4d84d7e69f
simlib.v: Add x-output tag 
Also a few extra cell help texts.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
ce6a7fe4fc
docs/util: Cells now have properties 
Properties are both an option:
```
.. cell:def:: $add
   :properties: is_evaluable
```
and a field:
```
.. cell:def:: $eqx

   :property x-aware:
   :property is_evaluable:
```

Properties as an option appear in the property index: linking a given property to all cells with that property; while properties as a field display with the cell.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
e3d939b719
Docs: Drop fifo.out and fifo.stat 
These two files can now be safely .gitignore'd.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
1a2401816a
Docs: Add cell title TODO 2024-10-15 07:35:41 +13:00
Krystine Sherwin
ed92374263
simlib.v: Update case equality operators to v2 
Also tag as x-aware cells and add titles.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
b1025dbaa6
cellhelp.py: Cells can have tags 
Tags are added to the list of properties when exporting to `cells.json`.
 2024-10-15 07:35:41 +13:00
Krystine Sherwin
9ce6952131
Docs: TODOs block, todos don't 2024-10-15 07:35:41 +13:00
Krystine Sherwin
f70a66f5b3
Docs: Assert cell has group 
Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.
 2024-10-15 07:35:40 +13:00
Krystine Sherwin
5c4f7b4deb
Docs: $eqx aka case equality 2024-10-15 07:35:40 +13:00
Krystine Sherwin
217c2a15dd
Docs: Add todos from JF 2024-10-15 07:35:40 +13:00