Mohamed Gaber
1d9fbb6143
misc: review feedback, remove MUL vestiges
2025-05-15 18:01:13 +03:00
Mohamed Gaber
46ba89059a
splitlarge: new pass to split wide arithmetic operators
...
Adds a new pass, `splitlarge`, that recursively divides $add/$sub
cells into smaller cells until each cell's width doesn't exceed a
given max_width (128 by default.) An $add/$sub cell's width for
this purpose is defined as the higher of the widths of its two
inputs.
A test was written in Tcl for it, which tests this matrix:
- cell: $add/$sub
- b: unsigned, signed
- a: unsigned, signed
This is the first test for a Silimate pass in Tcl and thus
`run-test.sh` was modified to include it.
2025-05-15 17:45:08 +03:00
Akash Levy
ba921e35ab
Fix NamedObject issue
2025-04-10 15:04:02 -07:00
Akash Levy
e241c9d513
Merge branch 'YosysHQ:main' into main
2025-04-10 14:28:10 -07:00
N. Engelhardt
3410e10ed5
Merge pull request #5000 from YosysHQ/krys/re_refactor_selections
2025-04-10 16:06:36 +00:00
Akash Levy
e391707d0a
Merge remote-tracking branch 'upstream/main'
2025-04-10 00:19:00 -07:00
github-actions[bot]
33c57937cd
Bump version
2025-04-10 00:22:42 +00:00
Emil J
a5e8f52ce5
Merge pull request #4976 from Logikable/main
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Support array ranges for identifiers in the Liberty parser.
2025-04-09 22:49:52 +02:00
Emily Schmidt
32ec5a9ccd
Revert "add dft_tag documentation"
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This reverts commit 2443facc46
2025-04-09 10:34:11 +01:00
Emily Schmidt
2443facc46
add dft_tag documentation
2025-04-09 10:18:25 +01:00
Miodrag Milanovic
a2c0847667
Next dev cycle
2025-04-09 08:21:08 +02:00
Miodrag Milanovic
fee39a3284
Release version 0.52
2025-04-09 07:38:42 +02:00
Akash Levy
3e24a3e248
Bump yosys to latest
2025-04-08 18:05:28 -07:00
github-actions[bot]
f602248a2e
Bump version
2025-04-09 00:22:49 +00:00
Miodrag Milanović
c261da4e79
Merge pull request #5001 from YosysHQ/micko/abc
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Update to latest ABC
2025-04-08 18:20:41 +02:00
Miodrag Milanovic
a9656455b1
Update to latest ABC
2025-04-08 17:39:41 +02:00
Miodrag Milanovic
406ee4c8d3
read_verilog_file_list: change short help message to start with lower case
2025-04-08 13:20:16 +02:00
Krystine Sherwin
078602d711
tests/arch/xilinx: Fix for warnings on boxes
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The two test scripts affected use boxed modules directly; under normal usage the warning shouldn't appear.
2025-04-08 16:58:59 +12:00
Krystine Sherwin
237e454131
design.cc: Fix selections when copying
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Use `Design::selected_modules()` directly, popping at the end instead of copying the selection.
Also default to a complete selection so that boxes work as before.
Simplify to using `RTLIL::SELECT_WHOLE_CMDERR` instead of doing it manually.
Also add tests for importing selections with boxes.
2025-04-08 16:35:12 +12:00
Krystine Sherwin
911a3ae759
setattr.cc: Use new selection helpers
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Also test they work as expected.
2025-04-08 15:34:48 +12:00
github-actions[bot]
857baf2031
Bump version
2025-04-08 00:22:31 +00:00
Krystine Sherwin
dbc2611dd6
test_select: Add and exercise test_select pass
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Developer facing, intended to check internal selection semantics work as expected. i.e. it would have revealed the bug in the now reverted PR.
2025-04-08 11:59:45 +12:00
Krystine Sherwin
f042c36898
rtlil.h: Extra comment on helper enums
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i.e. making explicit the ones that aren't intended for direct use.
2025-04-08 11:59:42 +12:00
Krystine Sherwin
f410f98d89
clean ignores boxes
2025-04-08 11:59:40 +12:00
Krystine Sherwin
1ef9908a85
rtlil.cc: Fix box checks in selected_modules
2025-04-08 11:59:36 +12:00
Krystine Sherwin
7d7ee5d9bf
rtlil.h: Fix selection ctor ordering
2025-04-08 11:59:32 +12:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
KrystalDelusion
bf386feba7
Merge pull request #4994 from marzoul/adrien-mux-x
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Fix mux mapping for xilinx techno when all inputs are x
2025-04-08 11:50:46 +12:00
Akash Levy
c0a6985adb
Merge branch 'YosysHQ:main' into main
2025-04-07 14:48:16 -07:00
KrystalDelusion
e08aeae1d0
Merge pull request #4989 from YosysHQ/krys/fix_4590
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opt_expr: Fix #4590
2025-04-08 08:30:18 +12:00
Akash Levy
de375d6542
Accommodate reversion and fix wreduce naming
2025-04-07 07:35:39 -07:00
Akash Levy
06c614a010
Merge branch 'YosysHQ:main' into main
2025-04-07 07:28:06 -07:00
Emil J
cc8fd3efc3
Merge pull request #4986 from jix/faster-liberty-caching
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Liberty file caching with new `libcache` command
2025-04-07 15:15:41 +02:00
Miodrag Milanović
1a820e259c
Merge pull request #4998 from YosysHQ/revert-4768-krys/refactor_selections
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Revert "Refactor full_selection"
2025-04-07 15:12:59 +02:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
Akash Levy
5c332df764
Bump abc
2025-04-07 00:43:58 -07:00
Akash Levy
6f44b93749
Bump abc
2025-04-07 00:24:31 -07:00
Adrien Prost-Boucle
3911a627a8
Clearer diff for the all-x corner case
2025-04-07 07:55:30 +02:00
Akash Levy
f86204b8ba
Fix pyosys for NamedObject
2025-04-06 22:52:59 -07:00
Akash Levy
0dab4308a3
Actual merge here
2025-04-06 18:53:43 -07:00
Akash Levy
69ce16c4a0
Bump abc to latest
2025-04-06 18:50:32 -07:00
Adrien Prost-Boucle
7a1729e609
Fix mux xilinx mapping when all inputs are x
2025-04-06 11:43:17 +02:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
github-actions[bot]
331952f78d
Bump version
2025-04-05 00:22:08 +00:00
KrystalDelusion
40c5694650
Merge pull request #4901 from akashlevy/pyosys_copy_abc
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Copy `abc` stuff for pyosys to enable use of the `abc` pass
2025-04-05 10:57:02 +13:00
Krystine Sherwin
d8a9ad6860
Add Selection::clear() method
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Use method in `select.cc` to reduce code duplication.
2025-04-05 10:56:01 +13:00
Krystine Sherwin
dab67f84da
rtlil.h: Document selections
2025-04-05 10:46:09 +13:00
Akash Levy
276800c39b
wreduce shifter signedness fix
2025-04-04 14:27:38 -07:00
Akash Levy
61715c2c28
Fix memory too large issue
2025-04-04 03:22:22 -07:00
Akash Levy
c3657eee6d
Fix Silimate tests
2025-04-04 03:21:53 -07:00
