mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-28 10:19:26 +00:00
Code Activity
10326 commits 121 branches 59 tags 72 MiB
Commit graph

398 commits

Author SHA1 Message Date
Eddie Hung
eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung
22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
Eddie Hung
eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Claire Wolf
589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Alberto Gonzalez
00d74f0b9c
Set Verilog source location for explicit blocks (begin ... end). 2020-04-17 06:23:03 +00:00
Alberto Gonzalez
10a814f978
Add Verilog source location information to AST_POSEDGE and AST_NEGEDGE nodes. 2020-04-17 06:16:59 +00:00
Alberto Gonzalez
9253497358
Add location information to AST_CONSTANT nodes. 2020-04-16 19:11:47 +00:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl 
support using previously declared types/localparams/parameters in package
 2020-04-14 12:40:00 +00:00
David Shah
0a178de1b3 verilog: Fix write to deleted object 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-12 18:49:09 +01:00
Jeff Wang
249876b614 support using previously declared types/localparams/params in package 
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
 2020-04-07 00:38:15 -04:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings 
IdString: use more ID::*, make them easier to use, speed up IdString::in()
 2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe 
Adding error message for when size (width) of number literal is zero
 2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
David Shah
c3997c77a5 verilog: Add location info for generate constructs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-01 18:47:20 +01:00
Diego H
c859bcf71b Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3 Adding error message for when size (width) of number literal is zero 2020-03-30 17:18:13 -06:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
Peter Crozier
f8c065ed1c Inline productions to follow house style. 2020-03-27 16:21:45 +00:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Peter Crozier
9a8a644ad1 Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
Peter Crozier
ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Peter Crozier
c06eda2504 Build pkg_user_types before parsing in case of changes in the design. 2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d Clear pkg_user_types if no packages following a 'design -reset-vlog'. 2020-03-22 18:20:46 -07:00
Peter
14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
Miodrag Milanović
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps 
Add dependency to verilog_lexer.cc
 2020-03-19 18:24:40 +01:00
Miodrag Milanovic
dc75ed7dac Add one mode dependency 2020-03-19 16:53:40 +01:00
N. Engelhardt
b473264a06
Merge pull request #1775 from huaixv/asserts_locations 
Add precise locations for asserts
 2020-03-19 13:12:18 +01:00
huaixv
cd82ccd258 Add precise locations for asserts 2020-03-19 10:22:07 +08:00
Alberto Gonzalez
6dd2024965
Add AST node source location information in a couple more parser rules. 2020-03-17 06:22:12 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Marcus Comstedt
5e94bf0291 refixed parsing of constant with comment between size and value 
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
 2020-03-11 18:21:44 +01:00
Eddie Hung
2d63bf5877 verilog: also set location for simple_behavioral_stmt 2020-03-10 10:29:24 -07:00
Alberto Gonzalez
da8270aa01
Set AST source locations in more parser rules. 2020-03-10 01:50:39 +00:00
Claire Wolf
a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
Claire Wolf
d59da5a4e4 Fix bison warning for "pure-parser" option 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-03 08:41:55 -08:00
Alberto Gonzalez
f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Eddie Hung
ea4bd161b6 verilog: add support for more delays than just rise/fall 2020-02-19 11:09:37 -08:00
Jeff Wang
d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Eddie Hung
d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung
6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Stefan Biereigel
b844b078db correct wire declaration grammar for #1614 2020-02-03 21:29:40 +01:00
David Shah
4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2 sv: Add lexing and parsing of .* (wildcard port conns) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00