mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

kernel/mem: Add model for wide ports.

Browse source 
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper.  Subsequent commits will gradually
add wide port support to various yosys passes.
This commit is contained in:
Marcelina Kościelnicka 2021-05-22 16:48:46 +02:00
parent 95a39d3425
commit ff9713dd86
2 changed files with 28 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/mem.h
View file

@ -29,6 +29,7 @@ struct MemRd {
bool removed;
dict<IdString, Const> attributes;
Cell *cell;
int wide_log2;
bool clk_enable, clk_polarity;
bool transparent;
SigSpec clk, en, addr, data;
@ -39,6 +40,7 @@ struct MemWr {
bool removed;
dict<IdString, Const> attributes;
Cell *cell;
int wide_log2;
bool clk_enable, clk_polarity;
std::vector<bool> priority_mask;
SigSpec clk, en, addr, data;