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https://github.com/YosysHQ/yosys
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opt_clean: refactor
This commit is contained in:
Emil J. Tywoniak
parent
e4c7a8fdab
commit
ff67ef6377
1 changed files with 318 additions and 258 deletions
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@ -18,282 +18,342 @@
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*/
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#include "kernel/ffinit.h"
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#include "kernel/yosys_common.h"
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#include "passes/opt/opt_clean/opt_clean.h"
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YOSYS_NAMESPACE_BEGIN
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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unsigned int hash_bit(const SigBit &bit) {
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return static_cast<unsigned int>(hash_ops<SigBit>::hash(bit).yield());
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}
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SigMap wire_sigmap(const RTLIL::Module* mod) {
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SigMap map;
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for (auto &it : mod->connections_) {
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for (int i = 0; i < GetSize(it.second); i++) {
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if (it.second[i].wire != nullptr)
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map.add(it.first[i], it.second[i]);
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}
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}
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return map;
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}
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struct WireDrivers;
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// Maps from a SigBit to a unique driver cell.
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struct WireDriver {
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using Accumulated = WireDrivers;
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SigBit bit;
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int driver_cell;
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};
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// Maps from a SigBit to one or more driver cells.
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struct WireDrivers {
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WireDrivers() : driver_cell(0) {}
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WireDrivers(WireDriver driver) : bit(driver.bit), driver_cell(driver.driver_cell) {}
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WireDrivers(SigBit bit) : bit(bit), driver_cell(0) {}
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WireDrivers(WireDrivers &&other) = default;
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class const_iterator {
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public:
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const_iterator(const WireDrivers &drivers, bool end)
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: driver_cell(drivers.driver_cell), in_extra_cells(end) {
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if (drivers.extra_driver_cells) {
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if (end) {
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extra_it = drivers.extra_driver_cells->end();
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} else {
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extra_it = drivers.extra_driver_cells->begin();
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}
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}
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}
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int operator*() const {
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if (in_extra_cells)
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return **extra_it;
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return driver_cell;
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}
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const_iterator& operator++() {
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if (in_extra_cells)
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++*extra_it;
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else
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in_extra_cells = true;
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return *this;
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}
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bool operator!=(const const_iterator &other) const {
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return !(*this == other);
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}
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bool operator==(const const_iterator &other) const {
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return in_extra_cells == other.in_extra_cells &&
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extra_it == other.extra_it;
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}
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private:
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std::optional<pool<int>::iterator> extra_it;
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int driver_cell;
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bool in_extra_cells;
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};
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const_iterator begin() const { return const_iterator(*this, false); }
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const_iterator end() const { return const_iterator(*this, true); }
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SigBit bit;
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int driver_cell;
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std::unique_ptr<pool<int>> extra_driver_cells;
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};
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struct WireDriversKeyEquality {
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bool operator()(const WireDrivers &a, const WireDrivers &b) const {
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return a.bit == b.bit;
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}
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};
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struct WireDriversCollisionHandler {
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void operator()(WireDrivers &incumbent, WireDrivers &new_value) const {
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log_assert(new_value.extra_driver_cells == nullptr);
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if (!incumbent.extra_driver_cells)
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incumbent.extra_driver_cells.reset(new pool<int>());
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incumbent.extra_driver_cells->insert(new_value.driver_cell);
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}
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};
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using Wire2Drivers = ShardedHashtable<WireDriver, WireDriversKeyEquality, WireDriversCollisionHandler>;
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struct CellAnalysis {
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Wire2Drivers wire2driver;
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dict<std::string, pool<int>> mem2cells;
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ShardedVector<Wire*> keep_wires;
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std::vector<std::atomic<bool>> unused;
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ConcurrentWorkQueue<int> cell_queue;
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ShardedVector<std::pair<SigBit, std::string>> driver_driver_logs;
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CellAnalysis(const SigMap& wire_map, AnalysisContext& actx, CleanRunContext &clean_ctx) : mem2cells(), keep_wires(actx.subpool), unused(actx.mod->cells_size()), cell_queue(actx.subpool.num_threads()), driver_driver_logs(actx.subpool) {
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Wire2Drivers::Builder wire2driver_builder(actx.subpool);
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ShardedVector<std::pair<std::string, int>> mem2cells_vector(actx.subpool);
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// Enqueue kept cells into cell_queue
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// Prepare input cone traversal from wire to driver cell as wire2driver
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// Prepare "input cone" traversal from memory to write port or meminit as mem2cells
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// Also check driver conflicts
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// Also mark cells unused to true unless keep (we override this later)
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actx.subpool.run([this, &wire_map, &mem2cells_vector, &wire2driver_builder, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(actx.mod->cells_size())) {
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Cell *cell = actx.mod->cell_at(i);
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if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
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mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
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for (auto &it2 : cell->connections()) {
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if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second) {
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if (raw_bit.wire == nullptr)
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continue;
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auto bit = actx.assign_map(raw_bit);
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if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
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std::string msg = stringf("Driver-driver conflict "
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"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
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log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
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driver_driver_logs.insert(ctx, {wire_map(raw_bit), msg});
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}
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if (bit.wire != nullptr)
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wire2driver_builder.insert(ctx, {{bit, i}, hash_bit(bit)});
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}
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}
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bool keep = clean_ctx.keep_cache.query(cell);
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unused[i].store(!keep, std::memory_order_relaxed);
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if (keep)
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cell_queue.push(ctx, i);
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}
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for (int i : ctx.item_range(actx.mod->wires_size())) {
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Wire *wire = actx.mod->wire_at(i);
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if (wire->port_output || wire->get_bool_attribute(ID::keep))
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keep_wires.insert(ctx, wire);
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}
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});
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// Finish by merging per-thread collected data
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actx.subpool.run([&wire2driver_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
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wire2driver_builder.process(ctx);
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});
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wire2driver = wire2driver_builder;
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for (std::pair<std::string, int> &mem2cell : mem2cells_vector)
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mem2cells[mem2cell.first].insert(mem2cell.second);
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}
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pool<SigBit> raw_wires_from_keep(const SigMap& sigmap, const SigMap& wire_map, int num_threads) {
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// Also enqueue cells that drive kept wires into cell_queue
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// and mark those cells as used
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// and mark all bits of those wires as used
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pool<SigBit> used_raw_bits;
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int i = 0;
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for (Wire *wire : keep_wires) {
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for (auto bit : sigmap(wire)) {
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const WireDrivers *drivers = wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_index : *drivers)
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if (unused[cell_index].exchange(false, std::memory_order_relaxed)) {
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ThreadIndex fake_thread_index = {i++ % num_threads};
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cell_queue.push(fake_thread_index, cell_index);
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}
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}
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for (auto raw_bit : SigSpec(wire))
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used_raw_bits.insert(wire_map(raw_bit));
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}
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return used_raw_bits;
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}
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void queue_cell_if_used(int cell_idx, const ParallelDispatchThreadPool::RunCtx &ctx) {
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if (unused[cell_idx].exchange(false, std::memory_order_relaxed))
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cell_queue.push(ctx, cell_idx);
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}
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void print_warnings(pool<SigBit>& used_raw_bits, const SigMap& wire_map, const RTLIL::Module* mod, CleanRunContext &clean_ctx) {
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if (!driver_driver_logs.empty()) {
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// We could do this in parallel but hopefully this is rare.
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for (auto [_, cell] : mod->cells_) {
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for (auto &[port, sig] : cell->connections()) {
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if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
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continue;
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for (auto raw_bit : wire_map(sig))
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used_raw_bits.insert(raw_bit);
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}
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}
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for (std::pair<SigBit, std::string> &it : driver_driver_logs) {
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if (used_raw_bits.count(it.first))
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log_warning("%s\n", it.second);
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}
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}
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}
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};
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struct MemAnalysis {
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std::vector<std::atomic<bool>> unused;
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dict<std::string, int> indices;
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MemAnalysis(RTLIL::Module* mod) : unused(mod->memories.size()), indices() {
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for (int i = 0; i < GetSize(mod->memories); ++i) {
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indices[mod->memories.element(i)->first.str()] = i;
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unused[i].store(true, std::memory_order_relaxed);
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}
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}
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/**
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* Functionally, analysis access is read-only
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*/
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void fixup_unused(CellAnalysis& analysis, AnalysisContext& actx, CleanRunContext &clean_ctx) {
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// Processes the cell queue in batches, traversing input cones by enqueuing more cells
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// Discover and mark used memories and cells
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actx.subpool.run([this, &analysis, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
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pool<SigBit> bits;
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pool<std::string> mems;
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while (true) {
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std::vector<int> cell_indices = analysis.cell_queue.pop_batch(ctx);
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if (cell_indices.empty())
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return;
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for (auto cell_index : cell_indices) {
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Cell *cell = actx.mod->cell_at(cell_index);
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for (auto &it : cell->connections())
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if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
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for (auto bit : actx.assign_map(it.second))
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bits.insert(bit);
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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std::string mem_id = cell->getParam(ID::MEMID).decode_string();
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if (indices.count(mem_id)) {
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int mem_index = indices[mem_id];
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// This is the actual fixup, everything else is just traversal
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if (unused[mem_index].exchange(false, std::memory_order_relaxed))
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mems.insert(mem_id);
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}
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}
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}
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for (auto bit : bits) {
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const WireDrivers *drivers = analysis.wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_idx : *drivers)
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analysis.queue_cell_if_used(cell_idx, ctx);
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}
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bits.clear();
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for (auto mem : mems) {
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if (analysis.mem2cells.count(mem) == 0)
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continue;
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for (int cell_idx : analysis.mem2cells.at(mem))
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analysis.queue_cell_if_used(cell_idx, ctx);
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}
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mems.clear();
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}
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});
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}
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};
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/**
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* Functionally, analysis access is read-only
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*/
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pool<Cell*> all_unused_cells(const Module *mod, CellAnalysis& analysis, ParallelDispatchThreadPool::Subpool &subpool) {
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pool<Cell*> unused_cells;
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{
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ShardedVector<int> sharded_unused_cells(subpool);
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subpool.run([mod, &analysis, &sharded_unused_cells](const ParallelDispatchThreadPool::RunCtx &ctx) {
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// Parallel destruction of `wire2driver`
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analysis.wire2driver.clear(ctx);
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for (int i : ctx.item_range(mod->cells_size()))
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if (analysis.unused[i].load(std::memory_order_relaxed))
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sharded_unused_cells.insert(ctx, i);
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});
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for (int cell_index : sharded_unused_cells)
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unused_cells.insert(mod->cell_at(cell_index));
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unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
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}
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return unused_cells;
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}
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void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cells, bool verbose, RmStats& stats) {
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for (auto cell : cells) {
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if (verbose)
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log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
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mod->design->scratchpad_set_bool("opt.did_something", true);
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if (cell->is_builtin_ff())
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ffinit.remove_init(cell->getPort(ID::Q));
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mod->remove(cell);
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stats.count_rm_cells++;
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}
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}
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void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbose) {
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for (const auto &it : mem_analysis.indices) {
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if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed))
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continue;
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RTLIL::IdString id(it.first);
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if (verbose)
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log_debug(" removing unused memory `%s'.\n", id.unescape());
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delete mod->memories.at(id);
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mod->memories.erase(id);
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}
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}
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PRIVATE_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx)
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{
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AnalysisContext actx(module, subpool);
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SigMap sigmap(module);
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FfInitVals ffinit;
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ffinit.set_parallel(&sigmap, subpool.thread_pool(), module);
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SigMap raw_sigmap;
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for (auto &it : module->connections_) {
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for (int i = 0; i < GetSize(it.second); i++) {
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if (it.second[i].wire != nullptr)
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raw_sigmap.add(it.first[i], it.second[i]);
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}
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}
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// Formerly known as raw_sigmap
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// TODO What exactly makes it "raw"? No constants on the rhs?
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// Otherwise, "raw" is used to mean "not sigmapped"
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SigMap wire_map = wire_sigmap(module);
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struct WireDrivers;
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// Maps from a SigBit to a unique driver cell.
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struct WireDriver {
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using Accumulated = WireDrivers;
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SigBit bit;
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int driver_cell;
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};
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// Maps from a SigBit to one or more driver cells.
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struct WireDrivers {
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WireDrivers() : driver_cell(0) {}
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WireDrivers(WireDriver driver) : bit(driver.bit), driver_cell(driver.driver_cell) {}
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WireDrivers(SigBit bit) : bit(bit), driver_cell(0) {}
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WireDrivers(WireDrivers &&other) = default;
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CellAnalysis analysis(wire_map, actx, clean_ctx);
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pool<SigBit> used_raw_bits = analysis.raw_wires_from_keep(sigmap, wire_map, subpool.num_threads());
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class const_iterator {
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public:
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const_iterator(const WireDrivers &drivers, bool end)
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: driver_cell(drivers.driver_cell), in_extra_cells(end) {
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if (drivers.extra_driver_cells) {
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if (end) {
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extra_it = drivers.extra_driver_cells->end();
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} else {
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extra_it = drivers.extra_driver_cells->begin();
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}
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}
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}
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int operator*() const {
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if (in_extra_cells)
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return **extra_it;
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return driver_cell;
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}
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const_iterator& operator++() {
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if (in_extra_cells)
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++*extra_it;
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else
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in_extra_cells = true;
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return *this;
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}
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bool operator!=(const const_iterator &other) const {
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return !(*this == other);
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}
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bool operator==(const const_iterator &other) const {
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return in_extra_cells == other.in_extra_cells &&
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extra_it == other.extra_it;
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}
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private:
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std::optional<pool<int>::iterator> extra_it;
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int driver_cell;
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bool in_extra_cells;
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};
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const_iterator begin() const { return const_iterator(*this, false); }
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const_iterator end() const { return const_iterator(*this, true); }
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SigBit bit;
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int driver_cell;
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std::unique_ptr<pool<int>> extra_driver_cells;
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};
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struct WireDriversKeyEquality {
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bool operator()(const WireDrivers &a, const WireDrivers &b) const {
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return a.bit == b.bit;
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}
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};
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struct WireDriversCollisionHandler {
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void operator()(WireDrivers &incumbent, WireDrivers &new_value) const {
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log_assert(new_value.extra_driver_cells == nullptr);
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if (!incumbent.extra_driver_cells)
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incumbent.extra_driver_cells.reset(new pool<int>());
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incumbent.extra_driver_cells->insert(new_value.driver_cell);
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}
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};
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using Wire2Drivers = ShardedHashtable<WireDriver, WireDriversKeyEquality, WireDriversCollisionHandler>;
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Wire2Drivers::Builder wire2driver_builder(subpool);
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ShardedVector<std::pair<std::string, int>> mem2cells_vector(subpool);
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ShardedVector<std::pair<SigBit, std::string>> driver_driver_logs(subpool);
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ShardedVector<Wire*> keep_wires(subpool);
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const RTLIL::Module *const_module = module;
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int num_threads = subpool.num_threads();
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ConcurrentWorkQueue<int> cell_queue(num_threads);
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std::vector<std::atomic<bool>> unused(const_module->cells_size());
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// Enqueue kept cells into cell_queue
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// Prepare input cone traversal from wire to driver cell as wire2driver
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// Prepare "input cone" traversal from memory to write port or meminit as mem2cells
|
||||
// Also check driver conflicts
|
||||
// Also mark cells unused to true unless keep (we override this later)
|
||||
subpool.run([&sigmap, &raw_sigmap, const_module, &mem2cells_vector, &driver_driver_logs, &keep_wires, &cell_queue, &wire2driver_builder, &clean_ctx, &unused](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(const_module->cells_size())) {
|
||||
Cell *cell = const_module->cell_at(i);
|
||||
if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
|
||||
mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
|
||||
|
||||
for (auto &it2 : cell->connections()) {
|
||||
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
|
||||
continue;
|
||||
for (auto raw_bit : it2.second) {
|
||||
if (raw_bit.wire == nullptr)
|
||||
continue;
|
||||
auto bit = sigmap(raw_bit);
|
||||
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
|
||||
std::string msg = stringf("Driver-driver conflict "
|
||||
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
|
||||
log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), const_module->name.unescape());
|
||||
driver_driver_logs.insert(ctx, {raw_sigmap(raw_bit), msg});
|
||||
}
|
||||
if (bit.wire != nullptr)
|
||||
wire2driver_builder.insert(ctx, {{bit, i}, hash_bit(bit)});
|
||||
}
|
||||
}
|
||||
bool keep = clean_ctx.keep_cache.query(cell);
|
||||
unused[i].store(!keep, std::memory_order_relaxed);
|
||||
if (keep)
|
||||
cell_queue.push(ctx, i);
|
||||
}
|
||||
for (int i : ctx.item_range(const_module->wires_size())) {
|
||||
Wire *wire = const_module->wire_at(i);
|
||||
if (wire->port_output || wire->get_bool_attribute(ID::keep))
|
||||
keep_wires.insert(ctx, wire);
|
||||
}
|
||||
});
|
||||
// Finish by merging per-thread collected data
|
||||
subpool.run([&wire2driver_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
wire2driver_builder.process(ctx);
|
||||
});
|
||||
Wire2Drivers wire2driver(wire2driver_builder);
|
||||
dict<std::string, pool<int>> mem2cells;
|
||||
for (std::pair<std::string, int> &mem2cell : mem2cells_vector)
|
||||
mem2cells[mem2cell.first].insert(mem2cell.second);
|
||||
|
||||
// Also enqueue cells that drive kept wires into cell_queue
|
||||
// and mark those cells as used
|
||||
// and mark all bits of those wires as used
|
||||
pool<SigBit> used_raw_bits;
|
||||
int i = 0;
|
||||
for (Wire *wire : keep_wires) {
|
||||
for (auto bit : sigmap(wire)) {
|
||||
const WireDrivers *drivers = wire2driver.find({{bit}, hash_bit(bit)});
|
||||
if (drivers != nullptr)
|
||||
for (int cell_index : *drivers)
|
||||
if (unused[cell_index].exchange(false, std::memory_order_relaxed)) {
|
||||
ThreadIndex fake_thread_index = {i++ % num_threads};
|
||||
cell_queue.push(fake_thread_index, cell_index);
|
||||
}
|
||||
}
|
||||
for (auto raw_bit : SigSpec(wire))
|
||||
used_raw_bits.insert(raw_sigmap(raw_bit));
|
||||
}
|
||||
|
||||
// Mark all memories as unused (we override this later)
|
||||
std::vector<std::atomic<bool>> mem_unused(module->memories.size());
|
||||
dict<std::string, int> mem_indices;
|
||||
for (int i = 0; i < GetSize(module->memories); ++i) {
|
||||
mem_indices[module->memories.element(i)->first.str()] = i;
|
||||
mem_unused[i].store(true, std::memory_order_relaxed);
|
||||
}
|
||||
|
||||
// Discover and mark used memories and cells
|
||||
// Processes the cell queue in batches, traversing input cones by enqueuing more cells
|
||||
subpool.run([const_module, &sigmap, &wire2driver, &mem2cells, &unused, &cell_queue, &mem_indices, &mem_unused, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
pool<SigBit> bits;
|
||||
pool<std::string> mems;
|
||||
while (true) {
|
||||
std::vector<int> cell_indices = cell_queue.pop_batch(ctx);
|
||||
if (cell_indices.empty())
|
||||
return;
|
||||
for (auto cell_index : cell_indices) {
|
||||
Cell *cell = const_module->cell_at(cell_index);
|
||||
for (auto &it : cell->connections())
|
||||
if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
|
||||
for (auto bit : sigmap(it.second))
|
||||
bits.insert(bit);
|
||||
|
||||
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
|
||||
std::string mem_id = cell->getParam(ID::MEMID).decode_string();
|
||||
if (mem_indices.count(mem_id)) {
|
||||
int mem_index = mem_indices[mem_id];
|
||||
if (mem_unused[mem_index].exchange(false, std::memory_order_relaxed))
|
||||
mems.insert(mem_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (auto bit : bits) {
|
||||
const WireDrivers *drivers = wire2driver.find({{bit}, hash_bit(bit)});
|
||||
if (drivers != nullptr)
|
||||
for (int cell_index : *drivers)
|
||||
if (unused[cell_index].exchange(false, std::memory_order_relaxed))
|
||||
cell_queue.push(ctx, cell_index);
|
||||
}
|
||||
bits.clear();
|
||||
|
||||
for (auto mem : mems) {
|
||||
if (mem2cells.count(mem) == 0)
|
||||
continue;
|
||||
for (int cell_index : mem2cells.at(mem))
|
||||
if (unused[cell_index].exchange(false, std::memory_order_relaxed))
|
||||
cell_queue.push(ctx, cell_index);
|
||||
}
|
||||
mems.clear();
|
||||
}
|
||||
});
|
||||
// Mark all memories as unused initially
|
||||
MemAnalysis mem_analysis(module);
|
||||
// then fix that by traversing design with analysis.cell_queue
|
||||
mem_analysis.fixup_unused(analysis, actx, clean_ctx);
|
||||
// mem_analysis is now correct
|
||||
// analysis and mem_analysis now are functionally finalized and read-only
|
||||
|
||||
// Set of all unused cells, built in parallel from unused by filtering for unused[i]==true
|
||||
pool<Cell*> unused_cells;
|
||||
{
|
||||
ShardedVector<int> sharded_unused_cells(subpool);
|
||||
subpool.run([const_module, &unused, &sharded_unused_cells, &wire2driver](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
// Parallel destruction of `wire2driver`
|
||||
wire2driver.clear(ctx);
|
||||
for (int i : ctx.item_range(const_module->cells_size()))
|
||||
if (unused[i].load(std::memory_order_relaxed))
|
||||
sharded_unused_cells.insert(ctx, i);
|
||||
});
|
||||
for (int cell_index : sharded_unused_cells)
|
||||
unused_cells.insert(const_module->cell_at(cell_index));
|
||||
unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
|
||||
}
|
||||
pool<Cell*> unused_cells = all_unused_cells(module, analysis, subpool);
|
||||
|
||||
for (auto cell : unused_cells) {
|
||||
if (clean_ctx.flags.verbose)
|
||||
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
|
||||
module->design->scratchpad_set_bool("opt.did_something", true);
|
||||
if (cell->is_builtin_ff())
|
||||
ffinit.remove_init(cell->getPort(ID::Q));
|
||||
module->remove(cell);
|
||||
clean_ctx.stats.count_rm_cells++;
|
||||
}
|
||||
|
||||
for (const auto &it : mem_indices) {
|
||||
if (!mem_unused[it.second].load(std::memory_order_relaxed))
|
||||
continue;
|
||||
RTLIL::IdString id(it.first);
|
||||
if (clean_ctx.flags.verbose)
|
||||
log_debug(" removing unused memory `%s'.\n", id.unescape());
|
||||
delete module->memories.at(id);
|
||||
module->memories.erase(id);
|
||||
}
|
||||
|
||||
if (!driver_driver_logs.empty()) {
|
||||
// We could do this in parallel but hopefully this is rare.
|
||||
for (auto [_, cell] : module->cells_) {
|
||||
for (auto &[port, sig] : cell->connections()) {
|
||||
if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
|
||||
continue;
|
||||
for (auto raw_bit : raw_sigmap(sig))
|
||||
used_raw_bits.insert(raw_bit);
|
||||
}
|
||||
}
|
||||
for (std::pair<SigBit, std::string> &it : driver_driver_logs) {
|
||||
if (used_raw_bits.count(it.first))
|
||||
log_warning("%s\n", it.second);
|
||||
}
|
||||
}
|
||||
remove_cells(module, ffinit, unused_cells, clean_ctx.flags.verbose, clean_ctx.stats);
|
||||
remove_mems(module, mem_analysis, clean_ctx.flags.verbose);
|
||||
analysis.print_warnings(used_raw_bits, wire_map, module, clean_ctx);
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue