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Added black box modules for all the 7-series design elements (as listed in ug953)

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This commit is contained in:
Clifford Wolf 2016-03-19 11:09:10 +01:00
parent ef4207d5ad
commit ff5c61b120
4 changed files with 3441 additions and 0 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -69,6 +69,7 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" begin:\n");
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
log(" read_verilog -lib +/xilinx/brams_bb.v\n");
log(" read_verilog -lib +/xilinx/drams_bb.v\n");
log(" hierarchy -check -top <top>\n");
@ -165,6 +166,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "begin"))
{
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));