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Put specify/endspecify inside ``

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Eddie Hung 2019-12-20 13:38:32 -08:00
parent 1482f32d53
commit ff2645ce0b
1 changed files with 4 additions and 4 deletions
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@ -454,10 +454,10 @@ Verilog Attributes and non-standard features
expressions over parameters and constant values are allowed). The intended expressions over parameters and constant values are allowed). The intended
use for this is synthesis-time DRC. use for this is synthesis-time DRC.
- There is limited support for converting specify .. endspecify statements to - There is limited support for converting ``specify`` .. ``endspecify``
special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
functionality. (By default specify .. endspecify blocks are ignored.) enable this functionality. (By default these blocks are ignored.)
Non-standard or SystemVerilog features for formal verification Non-standard or SystemVerilog features for formal verification