From fecea911ff5cc6440a2381605ec435bc42239822 Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 30 Apr 2026 11:35:03 +0100 Subject: [PATCH] synth_gatemate: add -abc_new option --- techlibs/gatemate/synth_gatemate.cc | 19 +++++++++++-- tests/arch/gatemate/add_sub.ys | 20 +++++++++++++ tests/arch/gatemate/adffs.ys | 44 +++++++++++++++++++++++++++++ tests/arch/gatemate/counter.ys | 25 ++++++++++++++++ tests/arch/gatemate/fsm.ys | 41 +++++++++++++++++++++++++++ tests/arch/gatemate/latches.ys | 20 +++++++++++++ tests/arch/gatemate/logic.ys | 23 +++++++++++++++ tests/arch/gatemate/luttrees.ys | 21 ++++++++++++++ tests/arch/gatemate/mul.ys | 26 +++++++++++++++++ tests/arch/gatemate/mux.ys | 37 ++++++++++++++++++++++++ 10 files changed, 273 insertions(+), 3 deletions(-) diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index 7726e7a15..7e968228e 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -69,7 +69,8 @@ struct SynthGateMatePass : public ScriptPass log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n"); log("\n"); log(" -luttree\n"); - log(" use new LUT tree mapping approach (EXPERIMENTAL).\n"); + log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n"); + log(" legacy p_r.\n"); log("\n"); log(" -dff\n"); log(" run 'abc' with -dff option\n"); @@ -77,6 +78,9 @@ struct SynthGateMatePass : public ScriptPass log(" -retime\n"); log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); + log(" -abc_new\n"); + log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n"); + log("\n"); log(" -noiopad\n"); log(" disable I/O buffer insertion (useful for hierarchical or \n"); log(" out-of-context flows).\n"); @@ -90,7 +94,7 @@ struct SynthGateMatePass : public ScriptPass } string top_opt, vlog_file, json_file; - bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf; + bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new; void clear_flags() override { @@ -108,6 +112,7 @@ struct SynthGateMatePass : public ScriptPass retime = false; noiopad = false; noclkbuf = false; + abc_new = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -182,6 +187,10 @@ struct SynthGateMatePass : public ScriptPass noclkbuf = true; continue; } + if (args[argidx] == "-abc_new") { + abc_new = true; + continue; + } break; } extra_args(args, argidx, design); @@ -312,7 +321,11 @@ struct SynthGateMatePass : public ScriptPass if (dff) { abc_args += " -dff"; } - run("abc " + abc_args, "(with -luttree)"); + if (abc_new) { + run("abc_new " + abc_args, "(with -luttree and -abc_new)"); + } else { + run("abc " + abc_args, "(with -luttree, without -abc_new)"); + } run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)"); run("gatemate_foldinv", "(with -luttree)"); run("techmap -map +/gatemate/inv_map.v", "(with -luttree)"); diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys index bf261ba5a..6720e08a0 100644 --- a/tests/arch/gatemate/add_sub.ys +++ b/tests/arch/gatemate/add_sub.ys @@ -1,9 +1,29 @@ read_verilog ../common/add_sub.v hierarchy -top top proc +design -save orig + equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:CC_ADDF select -assert-max 4 t:CC_LUT1 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D + +design -load orig + +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:CC_ADDF +select -assert-max 4 t:CC_LUT1 +select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D + +design -load orig + +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:CC_ADDF +select -assert-max 4 t:CC_LUT1 +select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys index b2ded6e9d..0a80a4b48 100644 --- a/tests/arch/gatemate/adffs.ys +++ b/tests/arch/gatemate/adffs.ys @@ -31,6 +31,28 @@ select -assert-count 1 t:CC_DFF select -assert-max 1 t:CC_LUT2 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D + design -load read hierarchy -top ndffnr proc @@ -41,3 +63,25 @@ select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_DFF select -assert-max 1 t:CC_LUT2 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D diff --git a/tests/arch/gatemate/counter.ys b/tests/arch/gatemate/counter.ys index 77ed858b3..8aa04e5cb 100644 --- a/tests/arch/gatemate/counter.ys +++ b/tests/arch/gatemate/counter.ys @@ -2,6 +2,9 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten + +design -save orig + equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -10,3 +13,25 @@ select -assert-count 8 t:CC_ADDF select -assert-count 1 t:CC_BUFG select -assert-count 8 t:CC_DFF select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D + +design -load orig + +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:CC_ADDF +select -assert-count 1 t:CC_BUFG +select -assert-count 8 t:CC_DFF +select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D + +design -load orig + +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:CC_ADDF +select -assert-count 1 t:CC_BUFG +select -assert-count 8 t:CC_DFF +select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys index 506862c90..8af1a0a47 100644 --- a/tests/arch/gatemate/fsm.ys +++ b/tests/arch/gatemate/fsm.ys @@ -3,6 +3,8 @@ hierarchy -top fsm proc flatten +design -save orig + equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad async2sync miter -equiv -make_assert -flatten gold gate miter @@ -18,3 +20,42 @@ select -assert-max 5 t:CC_LUT2 select -assert-max 6 t:CC_LUT3 select -assert-max 9 t:CC_LUT4 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D + +design -load orig + +equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree +async2sync +miter -equiv -make_assert -flatten gold gate miter +stat +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:CC_BUFG +select -assert-count 6 t:CC_DFF +select -assert-max 2 t:CC_LUT1 +select -assert-count 1 t:CC_LUT2 +select -assert-max 14 t:CC_L2T4 +select -assert-max 5 t:CC_L2T5 +select -assert-max 1 t:CC_MX2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D + +design -load orig + +equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new +async2sync +miter -equiv -make_assert -flatten gold gate miter +stat +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:CC_BUFG +select -assert-count 6 t:CC_DFF +select -assert-count 2 t:CC_LUT2 +select -assert-count 9 t:CC_L2T4 +select -assert-count 6 t:CC_L2T5 +select -assert-count 1 t:CC_MX2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys index 5f64c6db5..a044bf5d6 100644 --- a/tests/arch/gatemate/latches.ys +++ b/tests/arch/gatemate/latches.ys @@ -27,3 +27,23 @@ cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:CC_DLT select -assert-max 2 t:CC_LUT3 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_DLT +select -assert-max 2 t:CC_L2T4 +select -assert-none t:CC_DLT t:CC_L2T4 %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_DLT +select -assert-max 2 t:CC_L2T4 +select -assert-none t:CC_DLT t:CC_L2T4 %% t:* %D diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys index 026406bc8..e6204cdca 100644 --- a/tests/arch/gatemate/logic.ys +++ b/tests/arch/gatemate/logic.ys @@ -1,6 +1,9 @@ read_verilog ../common/logic.v hierarchy -top top proc + +design -save orig + equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -8,3 +11,23 @@ select -assert-max 1 t:CC_LUT1 select -assert-max 6 t:CC_LUT2 select -assert-max 2 t:CC_LUT4 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D + +design -load orig + +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_LUT1 +select -assert-count 6 t:CC_LUT2 +select -assert-count 2 t:CC_L2T4 +select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D + +design -load orig + +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_LUT1 +select -assert-count 6 t:CC_LUT2 +select -assert-count 2 t:CC_L2T4 +select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D diff --git a/tests/arch/gatemate/luttrees.ys b/tests/arch/gatemate/luttrees.ys index 545643226..f3a61ee60 100644 --- a/tests/arch/gatemate/luttrees.ys +++ b/tests/arch/gatemate/luttrees.ys @@ -11,3 +11,24 @@ cd luttrees # Constrain all select calls below inside the top module select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D +design -load read + +hierarchy -top luttrees +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd luttrees # Constrain all select calls below inside the top module + +select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% +select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D + +design -load read + +hierarchy -top luttrees +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd luttrees # Constrain all select calls below inside the top module + +select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% +select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys index ded5fe729..ef2255a76 100644 --- a/tests/arch/gatemate/mul.ys +++ b/tests/arch/gatemate/mul.ys @@ -31,3 +31,29 @@ select -assert-count 1 t:CC_BUFG select -assert-max 18 t:CC_LUT4 select -assert-count 18 t:CC_DFF select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D + +design -load read +hierarchy -top mul_unsigned_sync +proc +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned_sync # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_MULT +select -assert-count 1 t:CC_BUFG +select -assert-count 18 t:CC_LUT2 +select -assert-count 18 t:CC_MX2 +select -assert-count 18 t:CC_DFF +select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT2 t:CC_MX2 t:CC_DFF %% t:* %D + +design -load read +hierarchy -top mul_unsigned_sync +proc +# equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check (fails) +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned_sync # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_MULT +select -assert-count 1 t:CC_BUFG +select -assert-count 18 t:CC_LUT2 +select -assert-count 18 t:CC_MX2 +select -assert-count 18 t:CC_DFF +select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT2 t:CC_MX2 t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys index 320ff33d7..51c3b5daf 100644 --- a/tests/arch/gatemate/mux.ys +++ b/tests/arch/gatemate/mux.ys @@ -12,6 +12,25 @@ select -assert-max 2 t:CC_LUT4 select -assert-max 1 t:CC_MX2 select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 3 t:CC_MX2 +select -assert-none t:CC_MX2 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_LUT1 +select -assert-count 3 t:CC_MX2 +select -assert-none t:CC_LUT1 t:CC_MX2 %% t:* %D + design -load read hierarchy -top mux8 proc @@ -22,3 +41,21 @@ select -assert-max 1 t:CC_LUT3 select -assert-max 5 t:CC_LUT4 select -assert-max 1 t:CC_MX2 select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 7 t:CC_MX2 +select -assert-none t:CC_MX2 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 7 t:CC_MX2 +select -assert-none t:CC_MX2 %% t:* %D