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	Forgot backslashes
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		|  | @ -477,7 +477,7 @@ next_line: | ||||||
|                 RTLIL::Wire* wire = outputs[variable]; |                 RTLIL::Wire* wire = outputs[variable]; | ||||||
|                 log_assert(wire); |                 log_assert(wire); | ||||||
|                 log_assert(wire->port_output); |                 log_assert(wire->port_output); | ||||||
|                 if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) { |                 if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { | ||||||
|                     wire->port_output = false; |                     wire->port_output = false; | ||||||
|                     continue; |                     continue; | ||||||
|                 } |                 } | ||||||
|  |  | ||||||
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