mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-20 12:53:39 +00:00
Code Activity

Merge remote-tracking branch 'origin/master' into xc7dsp

Browse source
This commit is contained in:
Eddie Hung 2019-09-11 00:01:31 -07:00
commit feb3fa65a3
11 changed files with 397 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/opt/opt_expr.ys
View file

@ -204,7 +204,7 @@ endmodule
EOT
check
equiv_opt opt_expr -fine
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
@ -218,7 +218,7 @@ endmodule
EOT
check
equiv_opt opt_expr -fine
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
@ -232,7 +232,7 @@ endmodule
EOT
check
equiv_opt opt_expr
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
@ -246,7 +246,7 @@ endmodule
EOT
check
equiv_opt opt_expr
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
@ -260,7 +260,7 @@ endmodule
EOT
check
equiv_opt opt_expr
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=3 %i
@ -274,7 +274,7 @@ endmodule
EOT
check
equiv_opt opt_expr
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=10 %i
@ -288,6 +288,6 @@ endmodule
EOT
check
equiv_opt opt_expr -keepdc
equiv_opt -assert opt_expr -keepdc
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=13 %i

98
tests/techmap/wireinit.ys Normal file
View file

@ -0,0 +1,98 @@
read_verilog <<EOT
(* techmap_celltype = "$_DFF_P_" *)
module ffmap(...);
input D;
input C;
output Q;
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
endmodule
EOT
design -stash map
read_verilog <<EOT
(* techmap_celltype = "$_DFF_P_" *)
module ffmap(...);
input D;
input C;
output Q;
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
endmodule
EOT
design -stash map_noremove
read_verilog <<EOT
module ffbb (...);
parameter [0:0] INIT = 1'bx;
input D, C;
output Q;
endmodule
module top(...);
input clk;
input d;
output reg q0 = 0;
output reg q1 = 1;
output reg qx;
always @(posedge clk) begin
q0 <= d;
q1 <= d;
qx <= d;
end
endmodule
EOT
design -save ref
hierarchy -auto-top
proc
simplemap
techmap -map %map
clean
# Make sure the parameter was used properly.
select -assert-count 2 top/t:ffbb
select -set ff0 top/w:q0 %ci t:ffbb %i
select -set ffx top/w:qx %ci t:ffbb %i
select -assert-count 1 @ff0
select -assert-count 1 @ffx
select -assert-count 1 @ff0 r:INIT=1'b0 %i
select -assert-count 1 @ffx r:INIT=1'bx %i
select -assert-count 0 top/w:q1 %ci t:ffbb %i
# Make sure the init values are dropped from the wires iff mapping was performed.
select -assert-count 0 top/w:q0 a:init %i
select -assert-count 1 top/w:q1 a:init=1'b1 %i
select -assert-count 0 top/w:qx a:init %i
design -load ref
hierarchy -auto-top
proc
simplemap
techmap -map %map_noremove
clean
# Make sure the parameter was used properly.
select -assert-count 2 top/t:ffbb
select -set ff0 top/w:q0 %ci t:ffbb %i
select -set ffx top/w:qx %ci t:ffbb %i
select -assert-count 1 @ff0
select -assert-count 1 @ffx
select -assert-count 1 @ff0 r:INIT=1'b0 %i
select -assert-count 1 @ffx r:INIT=1'bx %i
select -assert-count 0 top/w:q1 %ci t:ffbb %i
# Make sure the init values are not dropped from the wires.
select -assert-count 1 top/w:q0 a:init=1'b0 %i
select -assert-count 1 top/w:q1 a:init=1'b1 %i
select -assert-count 0 top/w:qx a:init %i