From 54d43d85e302ca15d8dc0c05f935a9ed03821f31 Mon Sep 17 00:00:00 2001
From: Amelia Dobis <22934557+dobios@users.noreply.github.com>
Date: Fri, 19 Jun 2026 17:30:28 -0400
Subject: [PATCH 1/2] [docs] nit: usign the right acronym to refer to the right
 thing

Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
---
 docs/source/yosys_internals/formats/rtlil_rep.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst
index dbd69c7e4..580285e8a 100644
--- a/docs/source/yosys_internals/formats/rtlil_rep.rst
+++ b/docs/source/yosys_internals/formats/rtlil_rep.rst
@@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties:
 -  The wire name
 -  A list of attributes
 -  A width (buses are just wires with a width more than 1)
--  Bus direction (MSB to LSB or vice versa)
--  Lowest valid bit index (LSB or MSB depending on bus direction)
+-  Bus direction (MSb to LSb or vice versa)
+-  Lowest valid bit index (LSb or MSb depending on bus direction)
 -  If the wire is a port: port number and direction (input/output/inout)
 
 As with modules, the attributes can be Verilog attributes imported by the

From 41566a6b70871e9278cffe3df2704f2d06e12d6a Mon Sep 17 00:00:00 2001
From: Amelia Dobis <22934557+dobios@users.noreply.github.com>
Date: Fri, 19 Jun 2026 17:47:39 -0400
Subject: [PATCH 2/2] more typo found

---
 docs/source/yosys_internals/formats/rtlil_rep.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst
index 580285e8a..0fa09a3bc 100644
--- a/docs/source/yosys_internals/formats/rtlil_rep.rst
+++ b/docs/source/yosys_internals/formats/rtlil_rep.rst
@@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be
 used for coarse grain synthesis where the cells of the target architecture
 operate on entire signal vectors instead of single bit wires.
 
-In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
-the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
+In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either
+the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb;
 however, information from the HDL frontend is preserved so that the bus will be
 correctly indexed in error messages, backend output, constraint files, etc.