mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-01 17:03:19 +00:00
Code Activity

Added log_warning() API

Browse source
This commit is contained in:
Clifford Wolf 2014-11-09 10:44:23 +01:00
parent cb9e10b462
commit fe829bdbdc
15 changed files with 57 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/select.cc
View file

@ -532,7 +532,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
}
if (rem_objects == 0)
log("Warning: reached configured limit at `%s'.\n", arg.c_str());
log_warning("reached configured limit at `%s'.\n", arg.c_str());
}
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)

2
passes/fsm/fsm_detect.cc
View file

@ -43,7 +43,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
return true;
if (recursion_monitor.check_any(sig)) {
log("Warning: logic loop in mux tree at signal %s in module %s.\n",
log_warning("logic loop in mux tree at signal %s in module %s.\n",
log_signal(sig), RTLIL::id2cstr(module->name));
return false;
}

4
passes/hierarchy/submod.cc
View file

@ -85,7 +85,7 @@ struct SubmodWorker
for (auto &conn : cell->connections())
flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
} else {
log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
for (auto &conn : cell->connections())
flag_signal(conn.second, true, true, true, false, false);
}
@ -102,7 +102,7 @@ struct SubmodWorker
for (auto &conn : cell->connections())
flag_signal(conn.second, false, false, false, true, true);
if (flag_found_something)
log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
}
}

4
passes/proc/proc_dff.cc
View file

@ -333,12 +333,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (many_async_rules.size() > 0)
{
log("WARNING: Complex async reset for dff `%s'.\n", log_signal(sig));
log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
}
else if (!rstval.is_fully_const() && !ce.eval(rstval))
{
log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval));
log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
gen_dffsr(mod, insig, rstval, sig,
sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1,

2
passes/sat/eval.cc
View file

@ -277,7 +277,7 @@ struct VlogHammerReporter
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}

4
passes/sat/sat.cc
View file

@ -116,7 +116,7 @@ struct SatHelper
}
if (removed_bits.size())
log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
if (lhs.size()) {
log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
@ -327,7 +327,7 @@ struct SatHelper
show_drivers.insert(sigmap(p.second), c.second);
import_cell_counter++;
} else if (ignore_unknown_cells)
log("Warning: Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
else
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
}