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verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
This commit is contained in:
Zachary Snow
parent
98afe2b758
commit
fe74b0cd95
33 changed files with 783 additions and 262 deletions
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@ -41,10 +41,7 @@ generate
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wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
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// For $ge operation, start with the assumption that A and B are
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// equal (propagating this equality if A and B turn out to be so)
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam CI = 1'b1;
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else
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localparam CI = 1'b0;
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localparam CI = _TECHMAP_CELLTYPE_ == "$ge";
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$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
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_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
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end
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@ -81,12 +78,12 @@ generate
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assign Y = CO[LCU_WIDTH-1];
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end
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else begin
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if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
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localparam COST = 0;
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else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
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localparam COST = 1;
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else
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localparam COST = 2;
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localparam COST =
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_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
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? 0
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: (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
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? 1
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: 2);
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if (BUDGET < COST)
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
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@ -104,21 +101,21 @@ generate
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
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(* force_downto *)
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wire [LCU_WIDTH-1:0] P_, G_;
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if (LCU_WIDTH == 1) begin
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// Propagate only if all pairs are equal
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// (inconclusive evidence to say A >= B)
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wire P_ = P[0] & PP;
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assign P_ = P[0] & PP;
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// Generate if any comparisons call for it
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wire G_ = G[0] | GG;
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assign G_ = G[0] | GG;
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end
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else begin
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// Propagate only if all pairs are equal
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// (inconclusive evidence to say A >= B)
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(* force_downto *)
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wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
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assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
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// Generate if any comparisons call for it
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(* force_downto *)
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wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
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assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
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end
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if (AB_WIDTH == 1)
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$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
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@ -66,14 +66,12 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
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endfunction
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generate
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if (_TECHMAP_CELLTYPE_ == "$lt")
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localparam operation = 0;
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if (_TECHMAP_CELLTYPE_ == "$le")
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localparam operation = 1;
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if (_TECHMAP_CELLTYPE_ == "$gt")
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localparam operation = 2;
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam operation = 3;
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localparam operation =
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_TECHMAP_CELLTYPE_ == "$lt" ? 0 :
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_TECHMAP_CELLTYPE_ == "$le" ? 1 :
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_TECHMAP_CELLTYPE_ == "$gt" ? 2 :
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_TECHMAP_CELLTYPE_ == "$ge" ? 3 :
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-1;
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if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
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wire _TECHMAP_FAIL_ = 1;
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@ -121,7 +121,7 @@ module _80_mul (A, B, Y);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
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localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
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if (A_SIGNED && B_SIGNED) begin
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if (A_SIGNED && B_SIGNED) begin : blk
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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@ -129,7 +129,7 @@ module _80_mul (A, B, Y);
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin
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else begin : blk
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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@ -148,15 +148,15 @@ module _80_mul (A, B, Y);
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) mul (
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.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
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.B(B),
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.Y(partial[i])
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.Y(blk.partial[i])
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);
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// TODO: Currently a 'cascade' approach to summing the partial
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// products is taken here, but a more efficient 'binary
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// reduction' approach also exists...
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if (i == 0)
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assign partial_sum[i] = partial[i];
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assign blk.partial_sum[i] = blk.partial[i];
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else
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assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
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assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
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end
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\$__mul #(
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@ -168,17 +168,17 @@ module _80_mul (A, B, Y);
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) sliceA.last (
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.A(A[A_WIDTH-1 -: last_A_WIDTH]),
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.B(B),
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.Y(last_partial)
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.Y(blk.last_partial)
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);
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assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
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assign Y = partial_sum[n];
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assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
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assign Y = blk.partial_sum[n];
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
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localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
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localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
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if (A_SIGNED && B_SIGNED) begin
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if (A_SIGNED && B_SIGNED) begin : blk
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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@ -186,7 +186,7 @@ module _80_mul (A, B, Y);
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin
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else begin : blk
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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@ -205,15 +205,15 @@ module _80_mul (A, B, Y);
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) mul (
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.A(A),
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.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
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.Y(partial[i])
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.Y(blk.partial[i])
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);
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// TODO: Currently a 'cascade' approach to summing the partial
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// products is taken here, but a more efficient 'binary
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// reduction' approach also exists...
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if (i == 0)
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assign partial_sum[i] = partial[i];
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assign blk.partial_sum[i] = blk.partial[i];
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else
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assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
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assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
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end
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\$__mul #(
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@ -225,20 +225,24 @@ module _80_mul (A, B, Y);
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) mul_sliceB_last (
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.A(A),
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(last_partial)
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.Y(blk.last_partial)
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);
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assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
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assign Y = partial_sum[n];
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assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
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assign Y = blk.partial_sum[n];
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end
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else begin
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if (A_SIGNED)
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if (A_SIGNED) begin : blkA
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wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
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else
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end
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else begin : blkA
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wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
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if (B_SIGNED)
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end
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if (B_SIGNED) begin : blkB
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wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
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else
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end
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else begin : blkB
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wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
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end
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`DSP_NAME #(
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.A_SIGNED(A_SIGNED),
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@ -247,8 +251,8 @@ module _80_mul (A, B, Y);
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
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) _TECHMAP_REPLACE_ (
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.A(Aext),
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.B(Bext),
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.A(blkA.Aext),
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.B(blkB.Bext),
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.Y(Y)
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);
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end
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@ -254,6 +254,41 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
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wire [15:0] A1DATA_16, B1DATA_16;
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`define INSTANCE \
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\$__ICE40_RAM4K #( \
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.READ_MODE(MODE), \
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.WRITE_MODE(MODE), \
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.NEGCLK_R(!CLKPOL2), \
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.NEGCLK_W(!CLKPOL3), \
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.INIT_0(INIT_0), \
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.INIT_1(INIT_1), \
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.INIT_2(INIT_2), \
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.INIT_3(INIT_3), \
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.INIT_4(INIT_4), \
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.INIT_5(INIT_5), \
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.INIT_6(INIT_6), \
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.INIT_7(INIT_7), \
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.INIT_8(INIT_8), \
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.INIT_9(INIT_9), \
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.INIT_A(INIT_A), \
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.INIT_B(INIT_B), \
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.INIT_C(INIT_C), \
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.INIT_D(INIT_D), \
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.INIT_E(INIT_E), \
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.INIT_F(INIT_F) \
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) _TECHMAP_REPLACE_ ( \
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.RDATA(A1DATA_16), \
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.RADDR(A1ADDR_11), \
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.RCLK(CLK2), \
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.RCLKE(A1EN), \
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.RE(1'b1), \
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.WDATA(B1DATA_16), \
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.WADDR(B1ADDR_11), \
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.WCLK(CLK3), \
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.WCLKE(|B1EN), \
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.WE(1'b1) \
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);
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generate
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if (MODE == 1) begin
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assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
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@ -261,51 +296,23 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
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assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
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B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
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`include "brams_init1.vh"
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`INSTANCE
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end
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if (MODE == 2) begin
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assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
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assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
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`include "brams_init2.vh"
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`INSTANCE
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end
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if (MODE == 3) begin
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assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
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assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
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`include "brams_init3.vh"
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`INSTANCE
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end
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endgenerate
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\$__ICE40_RAM4K #(
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.READ_MODE(MODE),
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.WRITE_MODE(MODE),
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.NEGCLK_R(!CLKPOL2),
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.NEGCLK_W(!CLKPOL3),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA_16),
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.RADDR(A1ADDR_11),
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.RCLK(CLK2),
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.RCLKE(A1EN),
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.RE(1'b1),
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.WDATA(B1DATA_16),
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.WADDR(B1ADDR_11),
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.WCLK(CLK3),
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.WCLKE(|B1EN),
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.WE(1'b1)
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);
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`undef INSTANCE
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endmodule
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@ -151,6 +151,8 @@ generate if (`LUT_SIZE == 4) begin
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);
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end endgenerate
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assign X = S;
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end else begin
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localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
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@ -193,8 +195,8 @@ end else begin
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end
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end endgenerate
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end endgenerate
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assign X = S;
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end endgenerate
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endmodule
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