From 0a94441579f25f3661071692d2290c5c3b224a6a Mon Sep 17 00:00:00 2001 From: Abdelrahman Date: Tue, 26 Feb 2019 20:53:31 -0500 Subject: [PATCH 01/57] dockerize yosys --- Dockerfile | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Dockerfile diff --git a/Dockerfile b/Dockerfile new file mode 100644 index 000000000..3a4358335 --- /dev/null +++ b/Dockerfile @@ -0,0 +1,47 @@ +FROM ubuntu:16.04 as builder +LABEL author="Abdelrahman Hosny " + +RUN apt-get update && apt-get install -y build-essential \ + clang \ + bison \ + flex \ + libreadline-dev \ + gawk \ + tcl-dev \ + libffi-dev \ + git \ + graphviz \ + xdot \ + pkg-config \ + python3 + +COPY . / +RUN make && \ + make install + + +FROM ubuntu:16.04 +RUN apt-get update && apt-get install -y clang \ + bison \ + flex \ + libreadline-dev \ + gawk \ + tcl-dev \ + libffi-dev \ + git \ + graphviz \ + xdot \ + pkg-config \ + python3 +COPY --from=builder /yosys /build/yosys +COPY --from=builder /yosys-abc /build/yosys-abc +COPY --from=builder /yosys-config /build/yosys-config +COPY --from=builder /yosys-filterlib /build/yosys-filterlib +COPY --from=builder /yosys-smtbmc /build/yosys-smtbmc + +ENV PATH /build:$PATH + +RUN mkdir /data +WORKDIR /data + +ENTRYPOINT ["yosys"] From 3e3b115e0f3c9f0f9a37884cd3449bfbecfdc9f6 Mon Sep 17 00:00:00 2001 From: Abdelrahman Date: Tue, 26 Feb 2019 21:02:02 -0500 Subject: [PATCH 02/57] add dockerignore file --- .dockerignore | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 .dockerignore diff --git a/.dockerignore b/.dockerignore new file mode 100644 index 000000000..9910e9954 --- /dev/null +++ b/.dockerignore @@ -0,0 +1,13 @@ +.editorconfig +.gitignore +.gitmodules +.github +.git +Dockerfile +README.md +manual +CodingReadme +CodeOfConduct +.travis +.travis.yml + From ed358b237b597f2198c6e354e7c4084faf769d3a Mon Sep 17 00:00:00 2001 From: Abdelrahman Date: Fri, 1 Mar 2019 20:06:43 -0500 Subject: [PATCH 03/57] address review comments --- Dockerfile | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/Dockerfile b/Dockerfile index 3a4358335..3c7188d82 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,6 +1,6 @@ -FROM ubuntu:16.04 as builder +FROM ubuntu:18.04 as builder LABEL author="Abdelrahman Hosny " - +ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install -y build-essential \ clang \ bison \ @@ -10,29 +10,17 @@ RUN apt-get update && apt-get install -y build-essential \ tcl-dev \ libffi-dev \ git \ - graphviz \ - xdot \ pkg-config \ - python3 - + python3 && \ + rm -rf /var/lib/apt/lists COPY . / RUN make && \ make install +FROM ubuntu:18.04 +ENV DEBIAN_FRONTEND=noninteractive +RUN apt-get update && apt-get install -y libreadline-dev tcl-dev -FROM ubuntu:16.04 -RUN apt-get update && apt-get install -y clang \ - bison \ - flex \ - libreadline-dev \ - gawk \ - tcl-dev \ - libffi-dev \ - git \ - graphviz \ - xdot \ - pkg-config \ - python3 COPY --from=builder /yosys /build/yosys COPY --from=builder /yosys-abc /build/yosys-abc COPY --from=builder /yosys-config /build/yosys-config @@ -40,8 +28,6 @@ COPY --from=builder /yosys-filterlib /build/yosys-filterlib COPY --from=builder /yosys-smtbmc /build/yosys-smtbmc ENV PATH /build:$PATH - -RUN mkdir /data -WORKDIR /data - +RUN useradd -m yosys +USER yosys ENTRYPOINT ["yosys"] From ac10e7d96da4965751fd60a8dd42a8998c011c39 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 3 May 2019 03:10:43 +0300 Subject: [PATCH 04/57] Initial implementation of elaboration system tasks (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. --- frontends/ast/ast.cc | 1 + frontends/ast/ast.h | 4 ++- frontends/ast/genrtlil.cc | 1 + frontends/ast/simplify.cc | 47 ++++++++++++++++++++++++++++-- frontends/verilog/verilog_lexer.l | 5 ++++ frontends/verilog/verilog_parser.y | 11 ++++++- kernel/log.cc | 11 +++++++ kernel/log.h | 1 + tests/various/elab_sys_tasks.sv | 30 +++++++++++++++++++ tests/various/elab_sys_tasks.ys | 1 + 10 files changed, 107 insertions(+), 5 deletions(-) create mode 100644 tests/various/elab_sys_tasks.sv create mode 100644 tests/various/elab_sys_tasks.ys diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 9f88b08c1..d28345503 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -154,6 +154,7 @@ std::string AST::type2str(AstNodeType type) X(AST_GENIF) X(AST_GENCASE) X(AST_GENBLOCK) + X(AST_TECALL) X(AST_POSEDGE) X(AST_NEGEDGE) X(AST_EDGE) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 281cbe086..b3e6fbaa0 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -137,7 +137,8 @@ namespace AST AST_GENIF, AST_GENCASE, AST_GENBLOCK, - + AST_TECALL, + AST_POSEDGE, AST_NEGEDGE, AST_EDGE, @@ -233,6 +234,7 @@ namespace AST bool mem2reg_check(pool &mem2reg_set); void mem2reg_remove(pool &mem2reg_set, vector &delnodes); void meminfo(int &mem_width, int &mem_size, int &addr_bits); + bool check_elab_tasks(void); // additional functionality for evaluating constant functions struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b3a2a84be..d5e7d94ab 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -856,6 +856,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_GENVAR: case AST_GENFOR: case AST_GENBLOCK: + case AST_TECALL: case AST_GENIF: case AST_GENCASE: case AST_PACKAGE: diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 4d4b9dfe1..e6132995d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1146,7 +1146,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + if (!buf->children[i]->check_elab_tasks()) + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -1261,7 +1262,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + if (!buf->children[i]->check_elab_tasks()) + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -1340,7 +1342,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + if (!buf->children[i]->check_elab_tasks()) + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2969,6 +2972,44 @@ static void mark_memories_assign_lhs_complex(dict> & } } +// handle $info(), $warning(), $error(), $fatal() +// we don't do that in simplify() because we don't know +bool AstNode::check_elab_tasks(void) +{ + if (type == AST_TECALL) { + int sz = children.size(); + if (str == "$info") { + if (sz > 0) + log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_info(filename, linenum, "\n"); + } else if (str == "$warning") { + if (sz > 0) + log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_warning(filename, linenum, "\n"); + } else if (str == "$error") { + if (sz > 0) + log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "\n"); + } else if (str == "$fatal") { + // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() + // if no parameter is given, default value is 1 + // dollar_finish(sz ? children[0] : 1); + // perhaps create & use log_file_fatal() + if (sz > 0) + log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "FATAL.\n"); + } else { + log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str()); + } + return true; + } + return false; + +} // find memories that should be replaced by registers void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg_places, dict &mem2reg_candidates, dict &proc_flags, uint32_t &flags) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 6ef38252a..1c6810b47 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -301,6 +301,11 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(info|warning|error|fatal) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ELAB_TASK; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 40968d17a..1965f090e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -105,7 +105,7 @@ static void free_attr(std::map *al) bool boolean; } -%token TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL +%token TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL TOK_ELAB_TASK %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM @@ -1869,6 +1869,15 @@ gen_stmt: if ($6 != NULL) delete $6; ast_stack.pop_back(); + } | + TOK_ELAB_TASK { + AstNode *node = new AstNode(AST_TECALL); + node->str = *$1; + delete $1; + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } opt_arg_list ';'{ + ast_stack.pop_back(); }; gen_stmt_block: diff --git a/kernel/log.cc b/kernel/log.cc index 9a9104e26..d2a661bb0 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -278,6 +278,17 @@ void log_file_warning(const std::string &filename, int lineno, va_end(ap); } +void log_file_info(const std::string &filename, int lineno, + const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string prefix = stringf("%s:%d: Info: ", + filename.c_str(), lineno); + logv_warning_with_prefix(prefix.c_str(), format, ap); + va_end(ap); +} + YS_ATTRIBUTE(noreturn) static void logv_error_with_prefix(const char *prefix, const char *format, va_list ap) diff --git a/kernel/log.h b/kernel/log.h index e6afae716..3e1facae8 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); +void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); diff --git a/tests/various/elab_sys_tasks.sv b/tests/various/elab_sys_tasks.sv new file mode 100644 index 000000000..774d85b32 --- /dev/null +++ b/tests/various/elab_sys_tasks.sv @@ -0,0 +1,30 @@ +module test; +localparam X=1; +genvar i; +generate +if (X == 1) + $info("X is 1"); +if (X == 1) + $warning("X is 1"); +else + $error("X is not 1"); +case (X) + 1: $info("X is 1 in a case statement"); +endcase +//case (X-1) +// 1: $warn("X is 2"); +// default: $warn("X might be anything in a case statement"); +//endcase +for (i = 0; i < 3; i = i + 1) +begin + case(i) + 0: $info; + 1: $warning; + default: $info("default case statemnent"); + endcase +end + +$info("This is a standalone $info(). Next $info has no parameters"); +$info; +endgenerate +endmodule diff --git a/tests/various/elab_sys_tasks.ys b/tests/various/elab_sys_tasks.ys new file mode 100644 index 000000000..45bee3a60 --- /dev/null +++ b/tests/various/elab_sys_tasks.ys @@ -0,0 +1 @@ +read_verilog -sv elab_sys_tasks.sv From f06cb75b930d6ef5d8f4f12825ce0ef8f296ce17 Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 9 May 2019 12:37:31 +0200 Subject: [PATCH 05/57] initialize more registers in setundef -init --- passes/cmds/setundef.cc | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index f6949c820..5b43d528c 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -404,22 +404,29 @@ struct SetundefPass : public Pass { initwires.insert(wire); } - for (int wire_types = 0; wire_types < 2; wire_types++) - for (auto wire : module->wires()) - { - if (wire->name[0] == (wire_types ? '\\' : '$')) - next_wire: - continue; + for (int wire_types = 0; wire_types < 2; wire_types++) { + pool ffbitsToErase; + for (auto wire : module->wires()) { + if (wire->name[0] == (wire_types ? '\\' : '$')) { + next_wire: + continue; + } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) - goto next_wire; + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) { + goto next_wire; + } - for (auto bit : sigmap(wire)) - ffbits.erase(bit); + for (auto bit : sigmap(wire)) { + ffbitsToErase.insert(bit); + } - initwires.insert(wire); - } + initwires.insert(wire); + } + for (const auto &bit : ffbitsToErase) { + ffbits.erase(bit); + } + } for (auto wire : initwires) { From 9df04d7e7520884bfc40004bb131cfdb474061c7 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Wed, 22 May 2019 14:22:42 +0200 Subject: [PATCH 06/57] make lexer/parser aware of wand/wor net types --- frontends/ast/ast.h | 2 +- frontends/verilog/verilog_lexer.l | 2 ++ frontends/verilog/verilog_parser.y | 8 +++++++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 281cbe086..6c19dc7e6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -173,7 +173,7 @@ namespace AST // node content - most of it is unused in most node types std::string str; std::vector bits; - bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked; + bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked; int port_id, range_left, range_right; uint32_t integer; double realvalue; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 142d05d45..c763841c2 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -218,6 +218,8 @@ YOSYS_NAMESPACE_END "output" { return TOK_OUTPUT; } "inout" { return TOK_INOUT; } "wire" { return TOK_WIRE; } +"wor" { return TOK_WOR; } +"wand" { return TOK_WAND; } "reg" { return TOK_REG; } "integer" { return TOK_INTEGER; } "signed" { return TOK_SIGNED; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 132468f0c..8800705ac 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -139,7 +139,7 @@ struct specify_rise_fall { %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR -%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC +%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC @@ -485,6 +485,12 @@ wire_type_token_io: wire_type_token: TOK_WIRE { } | + TOK_WOR { + astbuf3->is_wor = true; + } | + TOK_WAND { + astbuf3->is_wand = true; + } | TOK_REG { astbuf3->is_reg = true; } | From 075a48d3fa69324d5b2700779a686fa46a69adb2 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Thu, 23 May 2019 10:16:41 +0200 Subject: [PATCH 07/57] implementation for assignments working --- frontends/ast/ast.cc | 3 ++ frontends/ast/ast.h | 1 + frontends/ast/genrtlil.cc | 93 +++++++++++++++++++++++++++++++++------ 3 files changed, 83 insertions(+), 14 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5623541b2..9c360efb6 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -51,6 +51,7 @@ namespace AST_INTERNAL { std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; + std::map wire_logic_map; AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; bool current_always_clocked; @@ -940,6 +941,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } + wire_logic_map = std::map(); + if (!defer) { bool blackbox_module = flag_lib; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 6c19dc7e6..7b1744b2e 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -327,6 +327,7 @@ namespace AST_INTERNAL extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; + extern std::map wire_logic_map; extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; extern bool current_always_clocked; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 379fed641..c60f8f5cc 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -163,6 +163,42 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const return wire; } +// helper function for creating RTLIL code for wand/wor declarations +static void wandwor2rtlil(AstNode *that, RTLIL::Wire *output_wire, bool gen_attributes = true) +{ + std::string type; + + if (that->is_wand) { + type = "$reduce_and"; + } else if (that->is_wor) { + type = "$reduce_or"; + } else { + log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n"); + } + + std::stringstream sstr; + sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); + + RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); + cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + + if (gen_attributes) + for (auto &attr : that->attributes) { + if (attr.second->type != AST_CONSTANT) + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + cell->attributes[attr.first] = attr.second->asAttrConst(); + } + + cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(0); + cell->setPort("\\A", RTLIL::SigSpec()); + + cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + cell->setPort("\\Y", output_wire); + + wire_logic_map[output_wire] = cell; +} + // helper class for converting AST always nodes to RTLIL processes struct AST_INTERNAL::ProcessGenerator { @@ -919,6 +955,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } + + if (is_wand || is_wor) { + if (wire->width > 1) + log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n"); + wandwor2rtlil(this, wire); + } + } break; @@ -1450,23 +1493,45 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // add entries to current_module->connections for assignments (outside of always blocks) case AST_ASSIGN: { + bool left_had_const = false; RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); - if (left.has_const()) { - RTLIL::SigSpec new_left, new_right; - for (int i = 0; i < GetSize(left); i++) - if (left[i].wire) { - new_left.append(left[i]); - new_right.append(right[i]); - } - log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" - " old assignment: %s = %s\n new assignment: %s = %s.\n", - log_signal(left), log_signal(right), - log_signal(new_left), log_signal(new_right)); - left = new_left; - right = new_right; - } + + RTLIL::SigSpec new_left, new_right; + for (int i = 0; i < GetSize(left); i++) + if (left[i].wire) { + std::map::iterator iter = wire_logic_map.find(left[i].wire); + if (iter == wire_logic_map.end()) + { + new_left.append(left[i]); + } else { + RTLIL::Cell *reduce_cell = iter->second; + RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); + int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); + log_warning("%d\n", reduce_cell_in.size()); + + RTLIL::Wire *new_reduce_input = current_module->addWire( + stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); + new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + reduce_cell_in.append(new_reduce_input); + reduce_cell->setPort("\\A", reduce_cell_in); + reduce_cell->fixup_parameters(); + new_left.append(new_reduce_input); + } + new_right.append(right[i]); + } else { + left_had_const = true; + } + + left = new_left; + right = new_right; current_module->connect(RTLIL::SigSig(left, right)); + + if (left_had_const) + log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" + " old assignment: %s = %s\n new assignment: %s = %s.\n", + log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); } break; From fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Thu, 23 May 2019 13:42:30 +0200 Subject: [PATCH 08/57] fix indentation across files --- frontends/ast/ast.cc | 6 +- frontends/ast/ast.h | 2 +- frontends/ast/genrtlil.cc | 128 ++++++++++++++++------------- frontends/verilog/verilog_parser.y | 4 +- 4 files changed, 80 insertions(+), 60 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 9c360efb6..963152588 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -51,7 +51,7 @@ namespace AST_INTERNAL { std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; - std::map wire_logic_map; + std::map wire_logic_map; AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; bool current_always_clocked; @@ -195,6 +195,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch is_logic = false; is_signed = false; is_string = false; + is_wand = false; + is_wor = false; was_checked = false; range_valid = false; range_swapped = false; @@ -941,7 +943,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } - wire_logic_map = std::map(); + wire_logic_map = std::map(); if (!defer) { diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 7b1744b2e..c2a7744c4 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -327,7 +327,7 @@ namespace AST_INTERNAL extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; - extern std::map wire_logic_map; + extern std::map wire_logic_map; extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; extern bool current_always_clocked; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index c60f8f5cc..7a6a2be6b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -166,37 +166,37 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const // helper function for creating RTLIL code for wand/wor declarations static void wandwor2rtlil(AstNode *that, RTLIL::Wire *output_wire, bool gen_attributes = true) { - std::string type; + std::string type; - if (that->is_wand) { - type = "$reduce_and"; - } else if (that->is_wor) { - type = "$reduce_or"; - } else { - log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n"); - } + if (that->is_wand) { + type = "$reduce_and"; + } else if (that->is_wor) { + type = "$reduce_or"; + } else { + log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n"); + } std::stringstream sstr; sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); - + if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - + cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(0); cell->setPort("\\A", RTLIL::SigSpec()); - + cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->setPort("\\Y", output_wire); - - wire_logic_map[output_wire] = cell; + + wire_logic_map[output_wire] = cell; } // helper class for converting AST always nodes to RTLIL processes @@ -956,12 +956,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes[attr.first] = attr.second->asAttrConst(); } - if (is_wand || is_wor) { - if (wire->width > 1) - log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n"); - wandwor2rtlil(this, wire); - } - + if (is_wand || is_wor) { + if (wire->width > 1) + log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n"); + wandwor2rtlil(this, wire); + } } break; @@ -1493,45 +1492,44 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // add entries to current_module->connections for assignments (outside of always blocks) case AST_ASSIGN: { - bool left_had_const = false; + bool left_had_const = false; RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); - RTLIL::SigSpec new_left, new_right; - for (int i = 0; i < GetSize(left); i++) - if (left[i].wire) { - std::map::iterator iter = wire_logic_map.find(left[i].wire); - if (iter == wire_logic_map.end()) - { - new_left.append(left[i]); - } else { - RTLIL::Cell *reduce_cell = iter->second; - RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); - int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); - log_warning("%d\n", reduce_cell_in.size()); + RTLIL::SigSpec new_left, new_right; + for (int i = 0; i < GetSize(left); i++) + if (left[i].wire) { + std::map::iterator iter = wire_logic_map.find(left[i].wire); + if (iter == wire_logic_map.end()) + { + new_left.append(left[i]); + } else { + RTLIL::Cell *reduce_cell = iter->second; + RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); + int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); - RTLIL::Wire *new_reduce_input = current_module->addWire( - stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); - new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - reduce_cell_in.append(new_reduce_input); - reduce_cell->setPort("\\A", reduce_cell_in); - reduce_cell->fixup_parameters(); - new_left.append(new_reduce_input); - } - new_right.append(right[i]); - } else { - left_had_const = true; - } + RTLIL::Wire *new_reduce_input = current_module->addWire( + stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); + new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + reduce_cell_in.append(new_reduce_input); + reduce_cell->setPort("\\A", reduce_cell_in); + reduce_cell->fixup_parameters(); + new_left.append(new_reduce_input); + } + new_right.append(right[i]); + } else { + left_had_const = true; + } - left = new_left; - right = new_right; + left = new_left; + right = new_right; current_module->connect(RTLIL::SigSig(left, right)); - - if (left_had_const) - log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" - " old assignment: %s = %s\n new assignment: %s = %s.\n", - log_signal(left), log_signal(right), - log_signal(new_left), log_signal(new_right)); + + if (left_had_const) + log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" + " old assignment: %s = %s\n new assignment: %s = %s.\n", + log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); } break; @@ -1576,14 +1574,34 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (child->type == AST_ARGUMENT) { RTLIL::SigSpec sig; - if (child->children.size() > 0) + RTLIL::SigSpec new_sig; + if (child->children.size() > 0) { sig = child->children[0]->genRTLIL(); + for (int i = 0; i < GetSize(sig); i++) { + std::map::iterator iter = wire_logic_map.find(sig[i].wire); + if (iter == wire_logic_map.end()) { + new_sig.append(sig[i]); + } else { + RTLIL::Cell *reduce_cell = iter->second; + RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); + int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); + + RTLIL::Wire *new_reduce_input = current_module->addWire( + stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); + new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + reduce_cell_in.append(new_reduce_input); + reduce_cell->setPort("\\A", reduce_cell_in); + reduce_cell->fixup_parameters(); + new_sig.append(new_reduce_input); + } + } + } if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++port_counter); - cell->setPort(buf, sig); + cell->setPort(buf, new_sig); } else { - cell->setPort(child->str, sig); + cell->setPort(child->str, new_sig); } continue; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8800705ac..8244a8f44 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -486,10 +486,10 @@ wire_type_token: TOK_WIRE { } | TOK_WOR { - astbuf3->is_wor = true; + astbuf3->is_wor = true; } | TOK_WAND { - astbuf3->is_wand = true; + astbuf3->is_wand = true; } | TOK_REG { astbuf3->is_reg = true; From c2caf85f7cbcbea4240b56a134e4c3e74189c62d Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Thu, 23 May 2019 13:42:42 +0200 Subject: [PATCH 09/57] add simple test case for wand/wor --- tests/various/wandwor.v | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 tests/various/wandwor.v diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v new file mode 100644 index 000000000..824f89683 --- /dev/null +++ b/tests/various/wandwor.v @@ -0,0 +1,35 @@ +module a(Q); + output wire Q; + + assign Q = 0; +endmodule + +module b(D); + input wire D; +endmodule + +module c; + wor D; + assign D = 1; + assign D = 0; + assign D = 1; + assign D = 0; + + + wand E; + wire E_wire = E; + + genvar i; + for (i = 0; i < 3; i = i + 1) + begin :genloop + a a_inst ( + .Q(E) + ); + + b b_inst ( + .D(E_wire) + ); + end + +endmodule + From 85de9d26c1118a83b01f62c450acecf3fd9077d6 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Thu, 23 May 2019 17:55:56 +0200 Subject: [PATCH 10/57] fix assignment of non-wires --- frontends/ast/genrtlil.cc | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 7a6a2be6b..047b0a81b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1500,8 +1500,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (int i = 0; i < GetSize(left); i++) if (left[i].wire) { std::map::iterator iter = wire_logic_map.find(left[i].wire); - if (iter == wire_logic_map.end()) - { + if (iter == wire_logic_map.end()) { new_left.append(left[i]); } else { RTLIL::Cell *reduce_cell = iter->second; @@ -1578,21 +1577,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (child->children.size() > 0) { sig = child->children[0]->genRTLIL(); for (int i = 0; i < GetSize(sig); i++) { - std::map::iterator iter = wire_logic_map.find(sig[i].wire); - if (iter == wire_logic_map.end()) { - new_sig.append(sig[i]); - } else { - RTLIL::Cell *reduce_cell = iter->second; - RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); - int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); + if (sig[i].wire) { + std::map::iterator iter = wire_logic_map.find(sig[i].wire); + if (iter == wire_logic_map.end()) { + new_sig.append(sig[i]); + } else { + RTLIL::Cell *reduce_cell = iter->second; + RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); + int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); - RTLIL::Wire *new_reduce_input = current_module->addWire( - stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); - new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - reduce_cell_in.append(new_reduce_input); - reduce_cell->setPort("\\A", reduce_cell_in); - reduce_cell->fixup_parameters(); - new_sig.append(new_reduce_input); + RTLIL::Wire *new_reduce_input = current_module->addWire( + stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); + new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + reduce_cell_in.append(new_reduce_input); + reduce_cell->setPort("\\A", reduce_cell_in); + reduce_cell->fixup_parameters(); + new_sig.append(new_reduce_input); + } + } else { + new_sig.append(sig[i]); } } } From ed625a3102233bf9c9af17e56575dc4a0ed8946c Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:00:22 +0200 Subject: [PATCH 11/57] move wand/wor resolution into hierarchy pass --- frontends/ast/genrtlil.cc | 111 +++++----------------------------- passes/hierarchy/hierarchy.cc | 78 +++++++++++++++++++++++- 2 files changed, 91 insertions(+), 98 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 047b0a81b..8094304e5 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -163,42 +163,6 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const return wire; } -// helper function for creating RTLIL code for wand/wor declarations -static void wandwor2rtlil(AstNode *that, RTLIL::Wire *output_wire, bool gen_attributes = true) -{ - std::string type; - - if (that->is_wand) { - type = "$reduce_and"; - } else if (that->is_wor) { - type = "$reduce_or"; - } else { - log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n"); - } - - std::stringstream sstr; - sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); - - if (gen_attributes) - for (auto &attr : that->attributes) { - if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); - cell->attributes[attr.first] = attr.second->asAttrConst(); - } - - cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(0); - cell->setPort("\\A", RTLIL::SigSpec()); - - cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\Y", output_wire); - - wire_logic_map[output_wire] = cell; -} - // helper class for converting AST always nodes to RTLIL processes struct AST_INTERNAL::ProcessGenerator { @@ -956,11 +920,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes[attr.first] = attr.second->asAttrConst(); } - if (is_wand || is_wor) { - if (wire->width > 1) - log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n"); - wandwor2rtlil(this, wire); - } + if (is_wand) wire->set_bool_attribute("\\wand"); + if (is_wor) wire->set_bool_attribute("\\wor"); } break; @@ -1492,43 +1453,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // add entries to current_module->connections for assignments (outside of always blocks) case AST_ASSIGN: { - bool left_had_const = false; RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); - - RTLIL::SigSpec new_left, new_right; - for (int i = 0; i < GetSize(left); i++) - if (left[i].wire) { - std::map::iterator iter = wire_logic_map.find(left[i].wire); - if (iter == wire_logic_map.end()) { + if (left.has_const()) { + RTLIL::SigSpec new_left, new_right; + for (int i = 0; i < GetSize(left); i++) + if (left[i].wire) { new_left.append(left[i]); - } else { - RTLIL::Cell *reduce_cell = iter->second; - RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); - int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); - - RTLIL::Wire *new_reduce_input = current_module->addWire( - stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); - new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - reduce_cell_in.append(new_reduce_input); - reduce_cell->setPort("\\A", reduce_cell_in); - reduce_cell->fixup_parameters(); - new_left.append(new_reduce_input); + new_right.append(right[i]); } - new_right.append(right[i]); - } else { - left_had_const = true; - } - - left = new_left; - right = new_right; - current_module->connect(RTLIL::SigSig(left, right)); - - if (left_had_const) log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" " old assignment: %s = %s\n new assignment: %s = %s.\n", log_signal(left), log_signal(right), log_signal(new_left), log_signal(new_right)); + left = new_left; + right = new_right; + } + current_module->connect(RTLIL::SigSig(left, right)); } break; @@ -1573,38 +1514,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (child->type == AST_ARGUMENT) { RTLIL::SigSpec sig; - RTLIL::SigSpec new_sig; - if (child->children.size() > 0) { + if (child->children.size() > 0) sig = child->children[0]->genRTLIL(); - for (int i = 0; i < GetSize(sig); i++) { - if (sig[i].wire) { - std::map::iterator iter = wire_logic_map.find(sig[i].wire); - if (iter == wire_logic_map.end()) { - new_sig.append(sig[i]); - } else { - RTLIL::Cell *reduce_cell = iter->second; - RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); - int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); - - RTLIL::Wire *new_reduce_input = current_module->addWire( - stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); - new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - reduce_cell_in.append(new_reduce_input); - reduce_cell->setPort("\\A", reduce_cell_in); - reduce_cell->fixup_parameters(); - new_sig.append(new_reduce_input); - } - } else { - new_sig.append(sig[i]); - } - } - } if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++port_counter); - cell->setPort(buf, new_sig); + cell->setPort(buf, sig); } else { - cell->setPort(child->str, new_sig); + cell->setPort(child->str, sig); } continue; } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 72bc2e133..013923816 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -562,7 +562,7 @@ struct HierarchyPass : public Pass { log("In parametric designs, a module might exists in several variations with\n"); log("different parameter values. This pass looks at all modules in the current\n"); log("design an re-runs the language frontends for the parametric modules as\n"); - log("needed.\n"); + log("needed. It also resolves assignments to wired logic data types (wand/wor).\n"); log("\n"); log(" -check\n"); log(" also check the design hierarchy. this generates an error when\n"); @@ -941,6 +941,61 @@ struct HierarchyPass : public Pass { std::set blackbox_derivatives; std::vector design_modules = design->modules(); + std::map wlogic_map; + + for (auto module : design_modules) + for (auto wire : module->wires()) + { + Cell *reduce = nullptr; + if (wire->get_bool_attribute("\\wand")) { + reduce = module->addCell( + stringf("$%s_reduce", wire->name.c_str()), "$reduce_and"); + } + if (wire->get_bool_attribute("\\wor")) { + reduce = module->addCell( + stringf("$%s_reduce", wire->name.c_str()), "$reduce_or"); + } + if (reduce) { + if (wire->width > 1) + log_error("Multi-bit wand/wor unsupported (%s)\n", + log_id(wire)); + + reduce->parameters["\\A_SIGNED"] = Const(0); + reduce->parameters["\\A_WIDTH"] = Const(0); + reduce->setPort("\\A", SigSpec()); + + reduce->parameters["\\Y_WIDTH"] = Const(1); + reduce->setPort("\\Y", wire); + wlogic_map[wire] = reduce; + } + } + + for (auto module : design_modules) { + std::vector new_connections; + for (auto &conn : module->connections()) + { + SigSpec sig = conn.first; + for (int i = 0; i < GetSize(sig); i++) { + Wire *sigwire = sig[i].wire; + if (sigwire == nullptr) + continue; + + if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) { + Cell *reduce = wlogic_map[sigwire]; + SigSpec reduce_in = reduce->getPort("\\A"); + int reduce_width = reduce->getParam("\\A_WIDTH").as_int(); + Wire *new_reduce_input = module->addWire( + stringf("%s_in%d", reduce->name.c_str(), reduce_width)); + reduce_in.append(new_reduce_input); + reduce->setPort("\\A", reduce_in); + reduce->fixup_parameters(); + sig[i] = new_reduce_input; + } + } + new_connections.push_back(SigSig(sig, conn.second)); + } + module->new_connections(new_connections); + } for (auto module : design_modules) for (auto cell : module->cells()) @@ -996,6 +1051,27 @@ struct HierarchyPass : public Pass { cell->setPort(conn.first, sig); } + for (int i = 0; i < GetSize(sig); i++) { + Wire *sigwire = sig[i].wire; + if (sigwire == nullptr) + continue; + + if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) { + if (w->port_output && !w->port_input) { + Cell *reduce = wlogic_map[sigwire]; + SigSpec reduce_in = reduce->getPort("\\A"); + int reduce_width = reduce->getParam("\\A_WIDTH").as_int(); + Wire *new_reduce_input = module->addWire( + stringf("$%s_in%d", reduce->name.c_str(), reduce_width)); + reduce_in.append(new_reduce_input); + reduce->setPort("\\A", reduce_in); + reduce->fixup_parameters(); + sig[i] = new_reduce_input; + } + } + } + cell->setPort(conn.first, sig); + if (w->port_output && !w->port_input && sig.has_const()) log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); From cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:01:44 +0200 Subject: [PATCH 12/57] remove leftovers from ast data structures --- frontends/ast/ast.cc | 3 --- frontends/ast/ast.h | 1 - 2 files changed, 4 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 963152588..44b8863f9 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -51,7 +51,6 @@ namespace AST_INTERNAL { std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; - std::map wire_logic_map; AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; bool current_always_clocked; @@ -943,8 +942,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } - wire_logic_map = std::map(); - if (!defer) { bool blackbox_module = flag_lib; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index c2a7744c4..6c19dc7e6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -327,7 +327,6 @@ namespace AST_INTERNAL extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; - extern std::map wire_logic_map; extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; extern bool current_always_clocked; From 7f11a732102c9e5c32871de9aad2de95b20d988f Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:07:12 +0200 Subject: [PATCH 13/57] update README.md with wand/wor information --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index efb74ef4e..73124898d 100644 --- a/README.md +++ b/README.md @@ -138,7 +138,7 @@ writing the design to the console in Yosys's internal format: yosys> write_ilang -elaborate design hierarchy: +elaborate design hierarchy and convert wand/wor nets to logic: yosys> hierarchy @@ -257,7 +257,7 @@ for them: - Non-synthesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 -- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types +- The ``tri``, ``triand`` and ``trior`` net types - The ``config`` and ``disable`` keywords and library map files From c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:10:39 +0200 Subject: [PATCH 14/57] remove port direction workaround from test case --- tests/various/wandwor.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v index 824f89683..d1dca6269 100644 --- a/tests/various/wandwor.v +++ b/tests/various/wandwor.v @@ -17,7 +17,6 @@ module c; wand E; - wire E_wire = E; genvar i; for (i = 0; i < 3; i = i + 1) @@ -27,7 +26,7 @@ module c; ); b b_inst ( - .D(E_wire) + .D(E) ); end From f68b658b4b88b9a71377d19d7d693f07eccf433e Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:45:54 +0200 Subject: [PATCH 15/57] reformat wand/wor test --- tests/various/wandwor.v | 43 ++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v index d1dca6269..fc072daa3 100644 --- a/tests/various/wandwor.v +++ b/tests/various/wandwor.v @@ -1,34 +1,33 @@ module a(Q); - output wire Q; - - assign Q = 0; + output wire Q = 0; endmodule module b(D); - input wire D; + input wire D; endmodule module c; - wor D; - assign D = 1; - assign D = 0; - assign D = 1; - assign D = 0; + // net definitions + wor D; + wand E; + // assignments to wired logic nets + assign D = 1; + assign D = 0; + assign D = 1; + assign D = 0; - wand E; - - genvar i; - for (i = 0; i < 3; i = i + 1) - begin :genloop - a a_inst ( - .Q(E) - ); - - b b_inst ( - .D(E) - ); - end + // assignments of wired logic nets to wires + wire F = E; + genvar i; + for (i = 0; i < 3; i = i + 1) + begin : genloop + // connection of module outputs + a a_inst (.Q(E)); + + // connection of module inputs + b b_inst (.D(E)); + end endmodule From 1575d962fa57ad06ad541cdac364893590e687f5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 28 May 2019 14:53:07 +0200 Subject: [PATCH 16/57] Moved pyosys block in Makefile --- Makefile | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 2f5da4110..0b99de001 100644 --- a/Makefile +++ b/Makefile @@ -22,14 +22,6 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYOSYS := 0 -ifeq ($(ENABLE_PYOSYS),1) -PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" -PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) -PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") -PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) -PYTHON_PREFIX := $(shell $(PYTHON_EXECUTABLE)-config --prefix) -PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages -endif # other configuration flags ENABLE_GCOV := 0 @@ -145,6 +137,22 @@ $(info $(subst $$--$$,$(newline),$(shell sed 's,^,[Makefile.conf] ,; s,$$,$$--$$ include Makefile.conf endif +ifeq ($(ENABLE_PYOSYS),1) +PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" +PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) +PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") +PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) +PYTHON_PREFIX := $(shell $(PYTHON_EXECUTABLE)-config --prefix) +PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages + +# Reload Makefile.conf to override python specific variables if defined +ifneq ($(wildcard Makefile.conf),) +$(info $(subst $$--$$,$(newline),$(shell sed 's,^,[Makefile.conf] ,; s,$$,$$--$$,;' < Makefile.conf | tr -d '\n' | sed 's,\$$--\$$$$,,'))) +include Makefile.conf +endif + +endif + ifeq ($(CONFIG),clang) CXX = clang LD = clang++ From 040b06cb370a8a0a6cdfdf49a605ee2eb113a01c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 28 May 2019 15:43:27 +0200 Subject: [PATCH 17/57] Remove info line in 2nd load of conf file --- Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile b/Makefile index 0b99de001..05b28f33d 100644 --- a/Makefile +++ b/Makefile @@ -147,7 +147,6 @@ PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages # Reload Makefile.conf to override python specific variables if defined ifneq ($(wildcard Makefile.conf),) -$(info $(subst $$--$$,$(newline),$(shell sed 's,^,[Makefile.conf] ,; s,$$,$$--$$,;' < Makefile.conf | tr -d '\n' | sed 's,\$$--\$$$$,,'))) include Makefile.conf endif From e3ebac44df5bcbd976c7f88f2192d69a337ac3bf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 16:42:50 +0200 Subject: [PATCH 18/57] Add actual wandwor test that is part of "make test" Signed-off-by: Clifford Wolf --- tests/simple/wandwor.v | 36 ++++++++++++++++++++++++++++++++++++ tests/various/wandwor.v | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) create mode 100644 tests/simple/wandwor.v delete mode 100644 tests/various/wandwor.v diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v new file mode 100644 index 000000000..34404aa26 --- /dev/null +++ b/tests/simple/wandwor.v @@ -0,0 +1,36 @@ +module wandwor_test0 (A, B, C, D, X, Y, Z); + input A, B, C, D; + output wor X; + output wand Y; + output Z; + + assign X = A, X = B, Y = C, Y = D; + foo foo_0 (C, D, X); + foo foo_1 (A, B, Y); + foo foo_2 (X, Y, Z); +endmodule + +module wandwor_test1 (A, B, C, D, X, Y, Z); + input [3:0] A, B, C, D; + output wor [3:0] X; + output wand [3:0] Y; + output Z; + + bar bar_inst ( + .I0({A, B}), + .I1({B, A}), + .O({X, Y}) + ); + + assign X = C, X = D; + assign Y = C, Y = D; + assign Z = ^{X,Y}; +endmodule + +module foo(input I0, I1, output O); + assign O = I0 ^ I1; +endmodule + +module bar(input [7:0] I0, I1, output [7:0] O); + assign O = I0 + I1; +endmodule diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v deleted file mode 100644 index fc072daa3..000000000 --- a/tests/various/wandwor.v +++ /dev/null @@ -1,33 +0,0 @@ -module a(Q); - output wire Q = 0; -endmodule - -module b(D); - input wire D; -endmodule - -module c; - // net definitions - wor D; - wand E; - - // assignments to wired logic nets - assign D = 1; - assign D = 0; - assign D = 1; - assign D = 0; - - // assignments of wired logic nets to wires - wire F = E; - - genvar i; - for (i = 0; i < 3; i = i + 1) - begin : genloop - // connection of module outputs - a a_inst (.Q(E)); - - // connection of module inputs - b b_inst (.D(E)); - end -endmodule - From ba2185ead89fdb6afeec6043ab18f2e045d80247 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 16:43:25 +0200 Subject: [PATCH 19/57] Refactor hierarchy wand/wor handling Signed-off-by: Clifford Wolf --- README.md | 2 +- kernel/rtlil.h | 1 + passes/hierarchy/hierarchy.cc | 281 +++++++++++++++++++--------------- 3 files changed, 163 insertions(+), 121 deletions(-) diff --git a/README.md b/README.md index 73124898d..19306cda3 100644 --- a/README.md +++ b/README.md @@ -138,7 +138,7 @@ writing the design to the console in Yosys's internal format: yosys> write_ilang -elaborate design hierarchy and convert wand/wor nets to logic: +elaborate design hierarchy: yosys> hierarchy diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 81ca93dce..8509670ff 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -601,6 +601,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; + inline int size() const { return width; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 013923816..24e64a9b2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -562,7 +562,8 @@ struct HierarchyPass : public Pass { log("In parametric designs, a module might exists in several variations with\n"); log("different parameter values. This pass looks at all modules in the current\n"); log("design an re-runs the language frontends for the parametric modules as\n"); - log("needed. It also resolves assignments to wired logic data types (wand/wor).\n"); + log("needed. It also resolves assignments to wired logic data types (wand/wor),\n"); + log("resolves positional module parameters, unroll array instances, and more.\n"); log("\n"); log(" -check\n"); log(" also check the design hierarchy. this generates an error when\n"); @@ -941,140 +942,180 @@ struct HierarchyPass : public Pass { std::set blackbox_derivatives; std::vector design_modules = design->modules(); - std::map wlogic_map; for (auto module : design_modules) - for (auto wire : module->wires()) { - Cell *reduce = nullptr; - if (wire->get_bool_attribute("\\wand")) { - reduce = module->addCell( - stringf("$%s_reduce", wire->name.c_str()), "$reduce_and"); - } - if (wire->get_bool_attribute("\\wor")) { - reduce = module->addCell( - stringf("$%s_reduce", wire->name.c_str()), "$reduce_or"); - } - if (reduce) { - if (wire->width > 1) - log_error("Multi-bit wand/wor unsupported (%s)\n", - log_id(wire)); + pool wand_wor_index; + dict wand_map, wor_map; + vector new_connections; - reduce->parameters["\\A_SIGNED"] = Const(0); - reduce->parameters["\\A_WIDTH"] = Const(0); - reduce->setPort("\\A", SigSpec()); - - reduce->parameters["\\Y_WIDTH"] = Const(1); - reduce->setPort("\\Y", wire); - wlogic_map[wire] = reduce; + for (auto wire : module->wires()) + { + if (wire->get_bool_attribute("\\wand")) { + wand_map[wire] = SigSpec(); + wand_wor_index.insert(wire); + } + if (wire->get_bool_attribute("\\wor")) { + wor_map[wire] = SigSpec(); + wand_wor_index.insert(wire); + } } - } - for (auto module : design_modules) { - std::vector new_connections; for (auto &conn : module->connections()) { - SigSpec sig = conn.first; - for (int i = 0; i < GetSize(sig); i++) { - Wire *sigwire = sig[i].wire; - if (sigwire == nullptr) - continue; + SigSig new_conn; + int cursor = 0; - if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) { - Cell *reduce = wlogic_map[sigwire]; - SigSpec reduce_in = reduce->getPort("\\A"); - int reduce_width = reduce->getParam("\\A_WIDTH").as_int(); - Wire *new_reduce_input = module->addWire( - stringf("%s_in%d", reduce->name.c_str(), reduce_width)); - reduce_in.append(new_reduce_input); - reduce->setPort("\\A", reduce_in); - reduce->fixup_parameters(); - sig[i] = new_reduce_input; - } - } - new_connections.push_back(SigSig(sig, conn.second)); - } - module->new_connections(new_connections); - } - - for (auto module : design_modules) - for (auto cell : module->cells()) - { - Module *m = design->module(cell->type); - - if (m == nullptr) - continue; - - if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { - IdString new_m_name = m->derive(design, cell->parameters, true); - if (new_m_name.empty()) - continue; - if (new_m_name != m->name) { - m = design->module(new_m_name); - blackbox_derivatives.insert(m); - } - } - - for (auto &conn : cell->connections()) - { - Wire *w = m->wire(conn.first); - - if (w == nullptr || w->port_id == 0) - continue; - - if (GetSize(conn.second) == 0) - continue; - - SigSpec sig = conn.second; - - if (!keep_portwidths && GetSize(w) != GetSize(conn.second)) + for (auto c : conn.first.chunks()) { - if (GetSize(w) < GetSize(conn.second)) - { - int n = GetSize(conn.second) - GetSize(w); - if (!w->port_input && w->port_output) - module->connect(sig.extract(GetSize(w), n), Const(0, n)); - sig.remove(GetSize(w), n); - } - else - { - int n = GetSize(w) - GetSize(conn.second); - if (w->port_input && !w->port_output) - sig.append(Const(0, n)); - else - sig.append(module->addWire(NEW_ID, n)); - } + Wire *w = c.wire; + SigSpec rhs = conn.second.extract(cursor, GetSize(c)); - if (!conn.second.is_fully_const() || !w->port_input || w->port_output) - log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), - log_id(conn.first), GetSize(conn.second), GetSize(sig)); - cell->setPort(conn.first, sig); - } - - for (int i = 0; i < GetSize(sig); i++) { - Wire *sigwire = sig[i].wire; - if (sigwire == nullptr) - continue; - - if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) { - if (w->port_output && !w->port_input) { - Cell *reduce = wlogic_map[sigwire]; - SigSpec reduce_in = reduce->getPort("\\A"); - int reduce_width = reduce->getParam("\\A_WIDTH").as_int(); - Wire *new_reduce_input = module->addWire( - stringf("$%s_in%d", reduce->name.c_str(), reduce_width)); - reduce_in.append(new_reduce_input); - reduce->setPort("\\A", reduce_in); - reduce->fixup_parameters(); - sig[i] = new_reduce_input; + if (wand_wor_index.count(w) == 0) { + new_conn.first.append(c); + new_conn.second.append(rhs); + } else { + if (wand_map.count(w)) { + SigSpec sig = SigSpec(State::S1, GetSize(w)); + sig.replace(c.offset, rhs); + wand_map.at(w).append(sig); + } else { + SigSpec sig = SigSpec(State::S0, GetSize(w)); + sig.replace(c.offset, rhs); + wor_map.at(w).append(sig); } } + cursor += GetSize(c); } - cell->setPort(conn.first, sig); + new_connections.push_back(new_conn); + } + module->new_connections(new_connections); - if (w->port_output && !w->port_input && sig.has_const()) - log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", - log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); + for (auto cell : module->cells()) + { + if (!cell->known()) + continue; + + for (auto &conn : cell->connections()) + { + if (!cell->output(conn.first)) + continue; + + SigSpec new_sig; + bool update_port = false; + + for (auto c : conn.second.chunks()) + { + Wire *w = c.wire; + + if (wand_wor_index.count(w) == 0) { + new_sig.append(c); + continue; + } + + Wire *t = module->addWire(NEW_ID, GetSize(c)); + new_sig.append(t); + update_port = true; + + if (wand_map.count(w)) { + SigSpec sig = SigSpec(State::S1, GetSize(w)); + sig.replace(c.offset, t); + wand_map.at(w).append(sig); + } else { + SigSpec sig = SigSpec(State::S0, GetSize(w)); + sig.replace(c.offset, t); + wor_map.at(w).append(sig); + } + } + + if (update_port) + cell->setPort(conn.first, new_sig); + } + } + + for (auto w : wand_wor_index) + { + bool wand = wand_map.count(w); + SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w); + + if (GetSize(sigs) == 0) + continue; + + if (GetSize(w) == 1) { + if (wand) + module->addReduceAnd(NEW_ID, sigs, w); + else + module->addReduceOr(NEW_ID, sigs, w); + continue; + } + + SigSpec s = sigs.extract(0, GetSize(w)); + for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) { + if (wand) + s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w))); + else + s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w))); + } + module->connect(w, s); + } + + for (auto cell : module->cells()) + { + Module *m = design->module(cell->type); + + if (m == nullptr) + continue; + + if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { + IdString new_m_name = m->derive(design, cell->parameters, true); + if (new_m_name.empty()) + continue; + if (new_m_name != m->name) { + m = design->module(new_m_name); + blackbox_derivatives.insert(m); + } + } + + for (auto &conn : cell->connections()) + { + Wire *w = m->wire(conn.first); + + if (w == nullptr || w->port_id == 0) + continue; + + if (GetSize(conn.second) == 0) + continue; + + SigSpec sig = conn.second; + + if (!keep_portwidths && GetSize(w) != GetSize(conn.second)) + { + if (GetSize(w) < GetSize(conn.second)) + { + int n = GetSize(conn.second) - GetSize(w); + if (!w->port_input && w->port_output) + module->connect(sig.extract(GetSize(w), n), Const(0, n)); + sig.remove(GetSize(w), n); + } + else + { + int n = GetSize(w) - GetSize(conn.second); + if (w->port_input && !w->port_output) + sig.append(Const(0, n)); + else + sig.append(module->addWire(NEW_ID, n)); + } + + if (!conn.second.is_fully_const() || !w->port_input || w->port_output) + log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), + log_id(conn.first), GetSize(conn.second), GetSize(sig)); + cell->setPort(conn.first, sig); + } + + if (w->port_output && !w->port_input && sig.has_const()) + log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", + log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); + } } } From cb285e4b87112779efe84a7b6c5ae4a76a69ae01 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 15:33:47 +0200 Subject: [PATCH 20/57] Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt_shiftmul.pmg | 15 +++++++++++---- tests/simple/peepopt.v | 4 ++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index fe861b728..6adab4e5f 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -1,4 +1,7 @@ pattern shiftmul +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// state shamt @@ -49,12 +52,16 @@ code if (GetSize(port(shift, \Y)) > const_factor) reject; + int factor_bits = ceil_log2(const_factor); + SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); + + if (GetSize(shamt) < factor_bits+GetSize(mul_din)) + reject; + did_something = true; log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); - int new_const_factor_log2 = ceil_log2(const_factor); - int new_const_factor = 1 << new_const_factor_log2; - + int new_const_factor = 1 << factor_bits; SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec old_a = port(shift, \A), new_a; int trunc = 0; @@ -73,7 +80,7 @@ code if (trunc > 0) new_a.remove(GetSize(new_a)-trunc, trunc); - SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)}; + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; if (param(shift, \B_SIGNED).as_bool()) new_b.append(State::S0); diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v index b27b9fe57..1bf427897 100644 --- a/tests/simple/peepopt.v +++ b/tests/simple/peepopt.v @@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in assign o = i[s*W+:W]; endmodule +module peepopt_shiftmul_1 (output y, input [2:0] w); +assign y = 1'b1 >> (w * (3'b110)); +endmodule + module peepopt_muldiv_0(input [1:0] i, output [1:0] o); wire [3:0] t; assign t = i * 3; From 14bd40cd3d760e22eeaf6f9622e210412e2b93a6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 29 May 2019 18:57:03 +0200 Subject: [PATCH 21/57] Aded one more load of .conf to support change of prefix --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index 05b28f33d..76dac48a5 100644 --- a/Makefile +++ b/Makefile @@ -46,6 +46,10 @@ OS := $(shell uname -s) PREFIX ?= /usr/local INSTALL_SUDO := +ifneq ($(wildcard Makefile.conf),) +include Makefile.conf +endif + BINDIR := $(PREFIX)/bin LIBDIR := $(PREFIX)/lib DATDIR := $(PREFIX)/share/yosys From 2faa1d0e80d213461d4403e36499aaaf1c8088b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 30 May 2019 10:03:54 +0200 Subject: [PATCH 22/57] Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 21a1bbbbe..33d2ac7a8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2016,6 +2016,9 @@ struct VerificPass : public Pass { // WARNING: instantiating unknown module 'XYZ' (VERI-1063) Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + // https://github.com/YosysHQ/yosys/issues/1055 + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + #ifndef DB_PRESERVE_INITIAL_VALUE # warning Verific was built without DB_PRESERVE_INITIAL_VALUE. #endif From 90ec2cda4217115fb91206a712befb3e6fa797e5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 May 2019 09:28:51 +0200 Subject: [PATCH 23/57] Fix "tee" handling of log_streams Signed-off-by: Clifford Wolf --- passes/cmds/tee.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index ee96ace86..1a44bdaec 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -52,7 +52,9 @@ struct TeePass : public Pass { void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector backup_log_files, files_to_close; + std::vector backup_log_streams; int backup_log_verbose_level = log_verbose_level; + backup_log_streams = log_streams; backup_log_files = log_files; size_t argidx; @@ -60,6 +62,7 @@ struct TeePass : public Pass { { if (args[argidx] == "-q" && files_to_close.empty()) { log_files.clear(); + log_streams.clear(); continue; } if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { @@ -89,6 +92,7 @@ struct TeePass : public Pass { for (auto cf : files_to_close) fclose(cf); log_files = backup_log_files; + log_streams = backup_log_streams; throw; } @@ -97,6 +101,7 @@ struct TeePass : public Pass { log_verbose_level = backup_log_verbose_level; log_files = backup_log_files; + log_streams = backup_log_streams; } } TeePass; From a6cadf6318f4eff6197d6c6f0e052c2417689f38 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 31 May 2019 12:24:12 +0200 Subject: [PATCH 24/57] Added support for parsing attributes on port connections. Signed-off-by: Maciej Kurc --- frontends/verilog/verilog_parser.y | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8244a8f44..82a1d9d39 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1532,27 +1532,27 @@ cell_port_list_rules: cell_port | cell_port_list_rules ',' cell_port; cell_port: - /* empty */ { + attr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); } | - expr { + attr expr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); - node->children.push_back($1); + node->children.push_back($2); } | - '.' TOK_ID '(' expr ')' { + attr '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - node->children.push_back($4); - delete $2; + node->children.push_back($5); + delete $3; } | - '.' TOK_ID '(' ')' { + attr '.' TOK_ID '(' ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - delete $2; + delete $3; }; always_stmt: From 36120fcc3064d0be20d5b9871a804b226471ceae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 2 Jun 2019 10:14:50 +0200 Subject: [PATCH 25/57] Only support Symbiotic EDA flavored Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 33d2ac7a8..2bf99e58e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -48,6 +48,14 @@ USING_YOSYS_NAMESPACE #include "VhdlUnits.h" #include "VeriLibrary.h" +#ifndef SYMBIOTIC_VERIFIC_API_VERSION +# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." +#endif + +#if SYMBIOTIC_VERIFIC_API_VERSION < 1 +# error "Please update your version of Symbiotic EDA flavored Verific." +#endif + #ifdef __clang__ #pragma clang diagnostic pop #endif From 5739cf52650ccb3627868d9c9d7e02888efad12b Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 3 Jun 2019 09:12:51 +0200 Subject: [PATCH 26/57] Added tests for attributes Signed-off-by: Maciej Kurc --- tests/simple/attrib01_module.v | 21 ++++++++++++++ tests/simple/attrib02_port_decl.v | 25 +++++++++++++++++ tests/simple/attrib03_parameter.v | 28 +++++++++++++++++++ tests/simple/attrib04_net_var.v | 32 ++++++++++++++++++++++ tests/simple/attrib05_port_conn.v.DISABLED | 21 ++++++++++++++ tests/simple/attrib06_operator_suffix.v | 23 ++++++++++++++++ tests/simple/attrib07_func_call.v.DISABLED | 21 ++++++++++++++ tests/simple/attrib08_mod_inst.v | 22 +++++++++++++++ tests/simple/attrib09_case.v | 26 ++++++++++++++++++ 9 files changed, 219 insertions(+) create mode 100644 tests/simple/attrib01_module.v create mode 100644 tests/simple/attrib02_port_decl.v create mode 100644 tests/simple/attrib03_parameter.v create mode 100644 tests/simple/attrib04_net_var.v create mode 100644 tests/simple/attrib05_port_conn.v.DISABLED create mode 100644 tests/simple/attrib06_operator_suffix.v create mode 100644 tests/simple/attrib07_func_call.v.DISABLED create mode 100644 tests/simple/attrib08_mod_inst.v create mode 100644 tests/simple/attrib09_case.v diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v new file mode 100644 index 000000000..adef34f5b --- /dev/null +++ b/tests/simple/attrib01_module.v @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v new file mode 100644 index 000000000..3505e7265 --- /dev/null +++ b/tests/simple/attrib02_port_decl.v @@ -0,0 +1,25 @@ +module bar(clk, rst, inp, out); + (* this_is_clock = 1 *) + input wire clk; + (* this_is_reset = 1 *) + input wire rst; + input wire inp; + (* an_output_register = 1*) + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + (* this_is_the_master_clock *) + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v new file mode 100644 index 000000000..562d225cd --- /dev/null +++ b/tests/simple/attrib03_parameter.v @@ -0,0 +1,28 @@ +module bar(clk, rst, inp, out); + + (* bus_width *) + parameter WIDTH = 2; + + (* an_attribute_on_localparam = 55 *) + localparam INCREMENT = 5; + + input wire clk; + input wire rst; + input wire [WIDTH-1:0] inp; + output reg [WIDTH-1:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp + INCREMENT; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [7:0] inp; + output wire [7:0] out; + + bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v new file mode 100644 index 000000000..8b5523406 --- /dev/null +++ b/tests/simple/attrib04_net_var.v @@ -0,0 +1,32 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + (* this_is_a_prescaler *) + reg [7:0] counter; + + (* temp_wire *) + wire out_val; + + always @(posedge clk) + counter <= counter + 1; + + assign out_val = inp ^ counter[4]; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= out_val; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED new file mode 100644 index 000000000..e20e66319 --- /dev/null +++ b/tests/simple/attrib05_port_conn.v.DISABLED @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); +endmodule + diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v new file mode 100644 index 000000000..e21173c58 --- /dev/null +++ b/tests/simple/attrib06_operator_suffix.v @@ -0,0 +1,23 @@ +module bar(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp_a + (* ripple_adder *) inp_b; + +endmodule + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + bar bar_instance (clk, rst, inp_a, inp_b, out); +endmodule + diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED new file mode 100644 index 000000000..f55ef2316 --- /dev/null +++ b/tests/simple/attrib07_func_call.v.DISABLED @@ -0,0 +1,21 @@ +function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + +endfunction + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + +endmodule + diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v new file mode 100644 index 000000000..c5a32234e --- /dev/null +++ b/tests/simple/attrib08_mod_inst.v @@ -0,0 +1,22 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + (* my_module_instance = 99 *) + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v new file mode 100644 index 000000000..8551bf9d0 --- /dev/null +++ b/tests/simple/attrib09_case.v @@ -0,0 +1,26 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output reg [1:0] out; + + always @(inp) + (* full_case, parallel_case *) + case(inp) + 2'd0: out <= 2'd3; + 2'd1: out <= 2'd2; + 2'd2: out <= 2'd1; + 2'd3: out <= 2'd0; + endcase + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output wire [1:0] out; + + bar bar_instance (clk, rst, inp, out); +endmodule + From 0ad50332d94dfd4e08dcb8e862ccdd91b4262eb2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 19:36:09 -0700 Subject: [PATCH 27/57] Execute techmap and arith_map simultaneously --- techlibs/xilinx/synth_xilinx.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c20cac09b..a569c20f4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -229,11 +229,6 @@ struct SynthXilinxPass : public ScriptPass run("dff2dffe"); run("opt -full"); - if (!vpr || help_mode) - run("techmap -map +/xilinx/arith_map.v"); - else - run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -242,7 +237,12 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - run("techmap"); + if (!vpr || help_mode) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + else + run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + + run("opt -fast"); } From 02973474df5b0b88b1744baa9cec703d089ff007 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 20:04:47 -0700 Subject: [PATCH 28/57] Remove extra newline --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a569c20f4..a293081f1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -242,7 +242,6 @@ struct SynthXilinxPass : public ScriptPass else run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - run("opt -fast"); } From b79bd5b3ca086718e308c75cbece0b07bbe48733 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 4 Jun 2019 10:42:42 +0200 Subject: [PATCH 29/57] Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. Signed-off-by: Maciej Kurc --- tests/various/attrib05_port_conn.v | 21 +++++++++++++++++++++ tests/various/attrib05_port_conn.ys | 2 ++ tests/various/attrib07_func_call.v | 21 +++++++++++++++++++++ tests/various/attrib07_func_call.ys | 2 ++ 4 files changed, 46 insertions(+) create mode 100644 tests/various/attrib05_port_conn.v create mode 100644 tests/various/attrib05_port_conn.ys create mode 100644 tests/various/attrib07_func_call.v create mode 100644 tests/various/attrib07_func_call.ys diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v new file mode 100644 index 000000000..e20e66319 --- /dev/null +++ b/tests/various/attrib05_port_conn.v @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); +endmodule + diff --git a/tests/various/attrib05_port_conn.ys b/tests/various/attrib05_port_conn.ys new file mode 100644 index 000000000..27a016733 --- /dev/null +++ b/tests/various/attrib05_port_conn.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib05_port_conn.v diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v new file mode 100644 index 000000000..f55ef2316 --- /dev/null +++ b/tests/various/attrib07_func_call.v @@ -0,0 +1,21 @@ +function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + +endfunction + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + +endmodule + diff --git a/tests/various/attrib07_func_call.ys b/tests/various/attrib07_func_call.ys new file mode 100644 index 000000000..774827651 --- /dev/null +++ b/tests/various/attrib07_func_call.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib07_func_call.v From c66d644b66f13d5cc54c78051bf97c0143d9940e Mon Sep 17 00:00:00 2001 From: Tux3 Date: Tue, 4 Jun 2019 10:45:41 +0200 Subject: [PATCH 30/57] README.md: Missing formatting for --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 19306cda3..94ea9538f 100644 --- a/README.md +++ b/README.md @@ -413,7 +413,7 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``'s?[bodh]``) support constant - expressions as . If the expression is not a simple identifier, it + expressions as ````. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in From dd3c333c0a206708ba2d821395fbf58a0e541f7b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 08:57:33 +0200 Subject: [PATCH 31/57] Remove yosys_banner() from python wrapper init, fixes #1056 Signed-off-by: Clifford Wolf --- misc/py_wrap_generator.py | 1 - 1 file changed, 1 deletion(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index 09f934040..9f2c72915 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -2060,7 +2060,6 @@ namespace YOSYS_PYTHON { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); - Yosys::yosys_banner(); } } From 8a6f9977f659d350cca936b45cb8b441d5a67eeb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 09:14:12 +0200 Subject: [PATCH 32/57] Suppress driver-driver conflict warning for unknown cell types, fixes #1065 Signed-off-by: Clifford Wolf --- passes/opt/opt_clean.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 7011d4602..cfb0f788a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -106,7 +106,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (raw_bit.wire == nullptr) continue; auto bit = sigmap(raw_bit); - if (bit.wire == nullptr) + if (bit.wire == nullptr && ct_all.cell_known(cell->type)) driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict " "for %s between cell %s.%s and constant %s in %s: Resolved using constant.", log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module))); From 4190d7c09477f4bdd35cbd7bf5388254764b2321 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 09:26:44 +0200 Subject: [PATCH 33/57] Fix typo in fmcombine log message, fixes #1063 Signed-off-by: Clifford Wolf --- passes/sat/fmcombine.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index f64d99dc2..00c098542 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -332,7 +332,7 @@ struct FmcombinePass : public Pass { gate_cell = module->cell(gate_name); if (gate_cell == nullptr) - log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); + log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); } else { @@ -351,7 +351,7 @@ struct FmcombinePass : public Pass { if (!gold_cell->parameters.empty()) log_cmd_error("Gold cell has unresolved instance parameters.\n"); if (!gate_cell->parameters.empty()) - log_cmd_error("Gold cell has unresolved instance parameters.\n"); + log_cmd_error("Gate cell has unresolved instance parameters.\n"); FmcombineWorker worker(design, gold_cell->type, opts); worker.generate(); From 6cc60ffd67784fa74e3ccbf9c2c273ad610e14b2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 09:53:06 +0200 Subject: [PATCH 34/57] Indent fix Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 42 +++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5b43d528c..e46d0a1dc 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -404,29 +404,31 @@ struct SetundefPass : public Pass { initwires.insert(wire); } - for (int wire_types = 0; wire_types < 2; wire_types++) { - pool ffbitsToErase; - for (auto wire : module->wires()) { - if (wire->name[0] == (wire_types ? '\\' : '$')) { - next_wire: - continue; - } + for (int wire_types = 0; wire_types < 2; wire_types++) + { + pool ffbitsToErase; + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) { + next_wire: + continue; + } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) { - goto next_wire; - } + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) { + goto next_wire; + } - for (auto bit : sigmap(wire)) { - ffbitsToErase.insert(bit); - } + for (auto bit : sigmap(wire)) { + ffbitsToErase.insert(bit); + } - initwires.insert(wire); - } - for (const auto &bit : ffbitsToErase) { - ffbits.erase(bit); - } - } + initwires.insert(wire); + } + for (const auto & bit : ffbitsToErase) { + ffbits.erase(bit); + } + } for (auto wire : initwires) { From b33176dafb03589952d3ac425e7cd8eeec61ea6a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 10:26:48 +0200 Subject: [PATCH 35/57] Major rewrite of wire selection in setundef -init Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 121 ++++++++++++++++++++++++++++++---------- 1 file changed, 90 insertions(+), 31 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e46d0a1dc..3eedc86b8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -393,53 +393,112 @@ struct SetundefPass : public Pass { ffbits.insert(bit); } - for (auto wire : module->wires()) + auto process_initwires = [&]() { - if (!wire->attributes.count("\\init")) - continue; + dict wire_weights; - for (auto bit : sigmap(wire)) - ffbits.erase(bit); + for (auto wire : initwires) + { + int weight = 0; - initwires.insert(wire); - } + for (auto bit : sigmap(wire)) + weight += ffbits.count(bit) ? +1 : -1; + + wire_weights[wire] = weight; + } + + initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); }); + + for (auto wire : initwires) + { + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + for (int i = 0; i < GetSize(wire); i++) { + SigBit bit = sigmap(SigBit(wire, i)); + if (initval[i] == State::Sx && ffbits.count(bit)) { + initval[i] = worker.next_bit(); + ffbits.erase(bit); + } + } + + if (initval.is_fully_undef()) + wire->attributes.erase("\\init"); + } + + initwires.clear(); + }; for (int wire_types = 0; wire_types < 2; wire_types++) { - pool ffbitsToErase; - for (auto wire : module->wires()) + // prioritize wires that already have an init attribute + if (!ffbits.empty()) { - if (wire->name[0] == (wire_types ? '\\' : '$')) { - next_wire: + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + if (!wire->attributes.count("\\init")) + continue; + + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + if (initval.is_fully_undef()) { + wire->attributes.erase("\\init"); + continue; + } + + for (int i = 0; i < GetSize(wire); i++) + if (initval[i] != State::Sx) + ffbits.erase(sigmap(SigBit(wire, i))); + + initwires.insert(wire); + } + + process_initwires(); + } + + // next consider wires that completely contain bits to be initialized + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) + goto next_wire; + + initwires.insert(wire); + + next_wire: continue; } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) { - goto next_wire; - } + process_initwires(); + } - for (auto bit : sigmap(wire)) { - ffbitsToErase.insert(bit); + // finally use whatever wire we can find. + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (ffbits.count(bit)) + initwires.insert(wire); } - initwires.insert(wire); - } - for (const auto & bit : ffbitsToErase) { - ffbits.erase(bit); + process_initwires(); } } - for (auto wire : initwires) - { - Const &initval = wire->attributes["\\init"]; - - for (int i = 0; i < GetSize(wire); i++) - if (GetSize(initval) <= i) - initval.bits.push_back(worker.next_bit()); - else if (initval.bits[i] == State::Sx) - initval.bits[i] = worker.next_bit(); - } + log_assert(ffbits.empty()); } module->rewrite_sigspecs(worker); From 03e0d3a17cf27858d16e0169614b6575c7dac538 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 5 Jun 2019 10:42:43 +0200 Subject: [PATCH 36/57] Fixed memory leak. Signed-off-by: Maciej Kurc --- frontends/verilog/verilog_parser.y | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 82a1d9d39..ccdab987f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1535,11 +1535,13 @@ cell_port: attr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); + free_attr($1); } | attr expr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); node->children.push_back($2); + free_attr($1); } | attr '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_ARGUMENT); @@ -1547,12 +1549,14 @@ cell_port: astbuf2->children.push_back(node); node->children.push_back($5); delete $3; + free_attr($1); } | attr '.' TOK_ID '(' ')' { AstNode *node = new AstNode(AST_ARGUMENT); node->str = *$3; astbuf2->children.push_back(node); delete $3; + free_attr($1); }; always_stmt: From feb2ddb52bd7ca590596e22f73a5d3c153907391 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 14:08:14 -0700 Subject: [PATCH 37/57] Fix typo in opt_rmdff --- passes/opt/opt_rmdff.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 2abffa2a9..eeb992a3e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -292,8 +292,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_q = dff->getPort("\\Q"); sig_c = dff->getPort("\\C"); sig_e = dff->getPort("\\E"); - val_cp = RTLIL::Const(dff->type[6] == 'P', 1); - val_ep = RTLIL::Const(dff->type[7] == 'P', 1); + val_cp = RTLIL::Const(dff->type[7] == 'P', 1); + val_ep = RTLIL::Const(dff->type[8] == 'P', 1); } else if (dff->type == "$ff") { sig_d = dff->getPort("\\D"); From dd134914cc93f7506504ad95aad438a468bb0fe8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 14:16:24 -0700 Subject: [PATCH 38/57] Error out if no top module given before 'sim' --- passes/sat/sim.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 53e248adf..4c3022c70 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -88,6 +88,8 @@ struct SimInstance SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) : shared(shared), module(module), instance(instance), parent(parent), sigmap(module) { + log_assert(module); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; @@ -848,6 +850,9 @@ struct SimPass : public Pass { if (design->full_selection()) { top_mod = design->top_module(); + + if (!top_mod) + log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n"); } else { auto mods = design->selected_whole_modules(); if (GetSize(mods) != 1) From fd8ef128bfdc01b6bcf90ca5a3426aac22811161 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 14:21:44 -0700 Subject: [PATCH 39/57] Missing doc for -tech xilinx in shregmap --- passes/techmap/shregmap.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 75eedfbcc..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -606,6 +606,9 @@ struct ShregmapPass : public Pass { log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); log("\n"); + log(" -tech xilinx\n"); + log(" map to xilinx dynamic-length shift registers.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { From f3a26730b610e1d80ca408e6913311bdfc82914c Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 6 Jun 2019 10:03:03 +0000 Subject: [PATCH 40/57] ECP5: implement all Diamond I/O buffer primitives. --- techlibs/ecp5/cells_map.v | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 6ab4b69f2..f6c71a03d 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED" module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +// Diamond I/O buffers +module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule +module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule +module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule +module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule + // For Diamond compatibility, FIXME: add all Diamond flipflop mappings module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001 From: tux3 Date: Wed, 5 Jun 2019 00:47:54 +0200 Subject: [PATCH 41/57] SystemVerilog support for implicit named port connections This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. --- frontends/verilog/verilog_parser.y | 26 +++++++++++++++++--------- tests/simple/run-test.sh | 3 ++- tests/tools/autotest.sh | 15 +++++++++++++-- tests/various/implicit_ports.sv | 19 +++++++++++++++++++ tests/various/implicit_ports.ys | 8 ++++++++ 5 files changed, 59 insertions(+), 12 deletions(-) create mode 100644 tests/various/implicit_ports.sv create mode 100644 tests/various/implicit_ports.ys diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8244a8f44..983445011 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -154,7 +154,7 @@ struct specify_rise_fall { %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list +%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port %type opt_label opt_sva_label tok_prim_wrapper hierarchical_id %type opt_signed opt_property unique_case_attr %type attr case_attr @@ -1541,18 +1541,26 @@ cell_port: astbuf2->children.push_back(node); node->children.push_back($1); } | - '.' TOK_ID '(' expr ')' { - AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; - astbuf2->children.push_back(node); - node->children.push_back($4); - delete $2; + named_port '(' ')' | // not connected + named_port '(' expr ')' { + ($1)->children.push_back($3); } | - '.' TOK_ID '(' ')' { + named_port { + // SV implied port + if (!sv_mode) + frontend_verilog_yyerror("Implicit .name port connection in port list (%s). This is not supported unless read_verilog is called with -sv!", $1->str.c_str()); + auto id_node = new AstNode(AST_IDENTIFIER); + id_node->str = ($1)->str; + ($1)->children.push_back(id_node); + }; + +named_port: + '.' TOK_ID { AstNode *node = new AstNode(AST_ARGUMENT); node->str = *$2; - astbuf2->children.push_back(node); delete $2; + astbuf2->children.push_back(node); + $$ = node; }; always_stmt: diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index aaa1cf940..967ac49f2 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then exit 1 fi -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v +shopt -s nullglob +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v} diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 920474a84..0a511f29c 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -89,6 +89,13 @@ done compile_and_run() { exe="$1"; output="$2"; shift 2 + ext=${1##*.} + if [ "$ext" == "sv" ]; then + language_gen="-g2012" + else + language_gen="-g2005" + fi + if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work @@ -99,7 +106,7 @@ compile_and_run() { /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@" /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench else - iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" + iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" vvp -n "$exe" fi } @@ -110,7 +117,7 @@ for fn do bn=${fn%.*} ext=${fn##*.} - if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then + if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then echo "Invalid argument: $fn" >&2 exit 1 fi @@ -123,6 +130,10 @@ do echo -n "Test: $bn " fi + if [ "$ext" == sv ]; then + frontend="$frontend -sv" + fi + rm -f ${bn}.{err,log,skip} mkdir -p ${bn}.out rm -rf ${bn}.out/* diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv new file mode 100644 index 000000000..6a766bd51 --- /dev/null +++ b/tests/various/implicit_ports.sv @@ -0,0 +1,19 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(output [2:0] alu_result, output cout); + wire [2:0] a = 3'b010, b = 3'b100; + wire cin = 1; + + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule + diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys new file mode 100644 index 000000000..7b4764921 --- /dev/null +++ b/tests/various/implicit_ports.ys @@ -0,0 +1,8 @@ +read_verilog -sv implicit_ports.sv +proc; opt + +flatten +select -module named_ports + +sat -verify -prove alu_result 6 +sat -verify -set-all-undef cout From d018e026142b9903a6f51b0a76ab109e86c4c59b Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Fri, 7 Jun 2019 09:47:33 +0200 Subject: [PATCH 42/57] remove boost/log/exceptions.hpp from wrapper generator --- misc/py_wrap_generator.py | 1 - 1 file changed, 1 deletion(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index 9f2c72915..9e5727499 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -2026,7 +2026,6 @@ def gen_wrappers(filename, debug_level_ = 0): #include #include #include -#include USING_YOSYS_NAMESPACE From a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 11:46:16 +0200 Subject: [PATCH 43/57] Cleanup tux3-implicit_named_connection Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 2 +- tests/{various => simple}/implicit_ports.sv | 5 +---- tests/various/implicit_ports.ys | 8 -------- 3 files changed, 2 insertions(+), 13 deletions(-) rename tests/{various => simple}/implicit_ports.sv (78%) delete mode 100644 tests/various/implicit_ports.ys diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2fffc7536..6d3afed0e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -154,7 +154,7 @@ struct specify_rise_fall { %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port +%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type opt_label opt_sva_label tok_prim_wrapper hierarchical_id %type opt_signed opt_property unique_case_attr %type attr case_attr diff --git a/tests/various/implicit_ports.sv b/tests/simple/implicit_ports.sv similarity index 78% rename from tests/various/implicit_ports.sv rename to tests/simple/implicit_ports.sv index 6a766bd51..8b0a6f386 100644 --- a/tests/various/implicit_ports.sv +++ b/tests/simple/implicit_ports.sv @@ -4,10 +4,8 @@ module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] r assign result = a + b; endmodule -module named_ports(output [2:0] alu_result, output cout); - wire [2:0] a = 3'b010, b = 3'b100; +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); wire cin = 1; - alu alu ( .a(a), .b, // Implicit connection is equivalent to .b(b) @@ -16,4 +14,3 @@ module named_ports(output [2:0] alu_result, output cout); .result(alu_result) ); endmodule - diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys deleted file mode 100644 index 7b4764921..000000000 --- a/tests/various/implicit_ports.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog -sv implicit_ports.sv -proc; opt - -flatten -select -module named_ports - -sat -verify -prove alu_result 6 -sat -verify -set-all-undef cout From 211d85cfcc1ae701bb9392347bcbb9750e3045b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 12:41:09 +0200 Subject: [PATCH 44/57] Fixes and cleanups in AST_TECALL handling Signed-off-by: Clifford Wolf --- frontends/ast/ast.h | 1 - frontends/ast/genrtlil.cc | 32 +++++++++++++++++++++++++- frontends/ast/simplify.cc | 47 +++------------------------------------ kernel/log.cc | 8 +++---- 4 files changed, 38 insertions(+), 50 deletions(-) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 93997ab86..b8cde060e 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -234,7 +234,6 @@ namespace AST bool mem2reg_check(pool &mem2reg_set); void mem2reg_remove(pool &mem2reg_set, vector &delnodes); void meminfo(int &mem_width, int &mem_size, int &addr_bits); - bool check_elab_tasks(void); // additional functionality for evaluating constant functions struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 60a087282..32ed401eb 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -858,7 +858,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_GENVAR: case AST_GENFOR: case AST_GENBLOCK: - case AST_TECALL: case AST_GENIF: case AST_GENCASE: case AST_PACKAGE: @@ -1576,6 +1575,37 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) delete always; } break; + case AST_TECALL: { + int sz = children.size(); + if (str == "$info") { + if (sz > 0) + log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_info(filename, linenum, "\n"); + } else if (str == "$warning") { + if (sz > 0) + log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_warning(filename, linenum, "\n"); + } else if (str == "$error") { + if (sz > 0) + log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "\n"); + } else if (str == "$fatal") { + // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() + // if no parameter is given, default value is 1 + // dollar_finish(sz ? children[0] : 1); + // perhaps create & use log_file_fatal() + if (sz > 0) + log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "FATAL.\n"); + } else { + log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str()); + } + } break; + case AST_FCALL: { if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 66fd243d3..e947125bf 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1146,8 +1146,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - if (!buf->children[i]->check_elab_tasks()) - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -1260,8 +1259,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - if (!buf->children[i]->check_elab_tasks()) - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -1340,8 +1338,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - if (!buf->children[i]->check_elab_tasks()) - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2971,44 +2968,6 @@ static void mark_memories_assign_lhs_complex(dict> & } } -// handle $info(), $warning(), $error(), $fatal() -// we don't do that in simplify() because we don't know -bool AstNode::check_elab_tasks(void) -{ - if (type == AST_TECALL) { - int sz = children.size(); - if (str == "$info") { - if (sz > 0) - log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str()); - else - log_file_info(filename, linenum, "\n"); - } else if (str == "$warning") { - if (sz > 0) - log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str()); - else - log_file_warning(filename, linenum, "\n"); - } else if (str == "$error") { - if (sz > 0) - log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str()); - else - log_file_error(filename, linenum, "\n"); - } else if (str == "$fatal") { - // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() - // if no parameter is given, default value is 1 - // dollar_finish(sz ? children[0] : 1); - // perhaps create & use log_file_fatal() - if (sz > 0) - log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str()); - else - log_file_error(filename, linenum, "FATAL.\n"); - } else { - log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str()); - } - return true; - } - return false; - -} // find memories that should be replaced by registers void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg_places, dict &mem2reg_candidates, dict &proc_flags, uint32_t &flags) diff --git a/kernel/log.cc b/kernel/log.cc index 9ce952cae..a7820950c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -277,7 +277,7 @@ void log_file_warning(const std::string &filename, int lineno, va_list ap; va_start(ap, format); std::string prefix = stringf("%s:%d: Warning: ", - filename.c_str(), lineno); + filename.c_str(), lineno); logv_warning_with_prefix(prefix.c_str(), format, ap); va_end(ap); } @@ -287,9 +287,9 @@ void log_file_info(const std::string &filename, int lineno, { va_list ap; va_start(ap, format); - std::string prefix = stringf("%s:%d: Info: ", - filename.c_str(), lineno); - logv_warning_with_prefix(prefix.c_str(), format, ap); + std::string fmt = stringf("%s:%d: Info: %s", + filename.c_str(), lineno, format); + logv(fmt.c_str(), ap); va_end(ap); } From f01a61f093528e5111e5dac8aedbf8c7c468be1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 13:12:25 +0200 Subject: [PATCH 45/57] Rename implicit_ports.sv test to implicit_ports.v Signed-off-by: Clifford Wolf --- tests/simple/{implicit_ports.sv => implicit_ports.v} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/simple/{implicit_ports.sv => implicit_ports.v} (100%) diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.v similarity index 100% rename from tests/simple/implicit_ports.sv rename to tests/simple/implicit_ports.v From 30abdaf3b2e0c3f21af0a7fdf2dc91ea59c7d54f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 08:30:39 -0700 Subject: [PATCH 46/57] Allow muxcover costs to be changed --- passes/techmap/muxcover.cc | 54 +++++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 12da9ed0c..32102436d 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -58,12 +58,21 @@ struct MuxcoverWorker bool use_mux16; bool nodecode; + int cost_mux2; + int cost_mux4; + int cost_mux8; + int cost_mux16; + MuxcoverWorker(Module *module) : module(module), sigmap(module) { use_mux4 = false; use_mux8 = false; use_mux16 = false; nodecode = false; + cost_mux2 = COST_MUX2; + cost_mux4 = COST_MUX4; + cost_mux8 = COST_MUX8; + cost_mux16 = COST_MUX16; decode_mux_counter = 0; } @@ -157,7 +166,7 @@ struct MuxcoverWorker if (std::get<2>(entry)) return 0; - return COST_MUX2 / GetSize(std::get<1>(entry)); + return cost_mux2 / GetSize(std::get<1>(entry)); } void implement_decode_mux(SigBit ctrl_bit) @@ -209,7 +218,7 @@ struct MuxcoverWorker mux.inputs.push_back(B); mux.selects.push_back(S1); - mux.cost += COST_MUX2; + mux.cost += cost_mux2; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); @@ -247,7 +256,7 @@ struct MuxcoverWorker mux.selects.push_back(S1); mux.selects.push_back(T1); - mux.cost += COST_MUX4; + mux.cost += cost_mux4; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -310,7 +319,7 @@ struct MuxcoverWorker mux.selects.push_back(T1); mux.selects.push_back(U1); - mux.cost += COST_MUX8; + mux.cost += cost_mux8; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -414,7 +423,7 @@ struct MuxcoverWorker mux.selects.push_back(U1); mux.selects.push_back(V1); - mux.cost += COST_MUX16; + mux.cost += cost_mux16; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -569,9 +578,11 @@ struct MuxcoverPass : public Pass { log("\n"); log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n"); log("\n"); - log(" -mux4, -mux8, -mux16\n"); - log(" Use the specified types of MUXes. If none of those options are used,\n"); - log(" the effect is the same as if all of them where used.\n"); + log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n"); + log(" Use the specified types of MUXes (with optional integer costs). If none\n"); + log(" of these options are given, the effect is the same as if all of them are.\n"); + log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4); + log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16); log("\n"); log(" -nodecode\n"); log(" Do not insert decoder logic. This reduces the number of possible\n"); @@ -587,23 +598,39 @@ struct MuxcoverPass : public Pass { bool use_mux8 = false; bool use_mux16 = false; bool nodecode = false; + int cost_mux4 = COST_MUX4; + int cost_mux8 = COST_MUX8; + int cost_mux16 = COST_MUX16; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-mux4") { + const auto &arg = args[argidx]; + if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { use_mux4 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux4 = atoi(arg.substr(5).c_str()); + } continue; } - if (args[argidx] == "-mux8") { + if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") { use_mux8 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux8 = atoi(arg.substr(5).c_str()); + } continue; } - if (args[argidx] == "-mux16") { + if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") { use_mux16 = true; + if (arg.size() > 6) { + if (arg[6] != '=') break; + cost_mux16 = atoi(arg.substr(6).c_str()); + } continue; } - if (args[argidx] == "-nodecode") { + if (arg == "-nodecode") { nodecode = true; continue; } @@ -623,6 +650,9 @@ struct MuxcoverPass : public Pass { worker.use_mux4 = use_mux4; worker.use_mux8 = use_mux8; worker.use_mux16 = use_mux16; + worker.cost_mux4 = cost_mux4; + worker.cost_mux8 = cost_mux8; + worker.cost_mux16 = cost_mux16; worker.nodecode = nodecode; worker.run(); } From 1b113a05742377f5b18d52bc5bf50b1991e88c19 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:05:25 -0700 Subject: [PATCH 47/57] Add symbols to AIGER test inputs for ABC --- tests/aiger/and.aig | 3 --- tests/aiger/{and.aag => and_.aag} | 3 +++ tests/aiger/and_.aig | 5 +++++ tests/aiger/buffer.aag | 2 ++ tests/aiger/buffer.aig | 2 ++ tests/aiger/cnt1.aag | 1 + tests/aiger/cnt1.aig | 1 + tests/aiger/cnt1e.aag | 1 + tests/aiger/cnt1e.aig | 3 ++- tests/aiger/false.aag | 1 + tests/aiger/false.aig | 1 + tests/aiger/inverter.aag | 2 ++ tests/aiger/inverter.aig | 2 ++ tests/aiger/notcnt1e.aag | 1 + tests/aiger/notcnt1e.aig | 3 ++- tests/aiger/or.aig | 3 --- tests/aiger/{or.aag => or_.aag} | 3 +++ tests/aiger/or_.aig | 5 +++++ tests/aiger/toggle.aag | 2 ++ tests/aiger/toggle.aig | 2 ++ tests/aiger/true.aag | 1 + tests/aiger/true.aig | 1 + 22 files changed, 40 insertions(+), 8 deletions(-) delete mode 100644 tests/aiger/and.aig rename tests/aiger/{and.aag => and_.aag} (55%) create mode 100644 tests/aiger/and_.aig delete mode 100644 tests/aiger/or.aig rename tests/aiger/{or.aag => or_.aag} (55%) create mode 100644 tests/aiger/or_.aig diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig deleted file mode 100644 index da0fa0719..000000000 --- a/tests/aiger/and.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -6 - \ No newline at end of file diff --git a/tests/aiger/and.aag b/tests/aiger/and_.aag similarity index 55% rename from tests/aiger/and.aag rename to tests/aiger/and_.aag index d1ef2c5a5..cadd505f0 100644 --- a/tests/aiger/and.aag +++ b/tests/aiger/and_.aag @@ -3,3 +3,6 @@ aag 3 2 0 1 1 4 6 6 2 4 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/and_.aig b/tests/aiger/and_.aig new file mode 100644 index 000000000..13c7a0c17 --- /dev/null +++ b/tests/aiger/and_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +6 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag index 94a6fb1ed..211106ed6 100644 --- a/tests/aiger/buffer.aag +++ b/tests/aiger/buffer.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 2 +i0 pi0 +o0 po0 diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig index 0c715fdeb..01df6f1cf 100644 --- a/tests/aiger/buffer.aig +++ b/tests/aiger/buffer.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 2 +i0 pi0 +o0 po0 diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag index ce4f28fcb..75598862c 100644 --- a/tests/aiger/cnt1.aag +++ b/tests/aiger/cnt1.aag @@ -1,3 +1,4 @@ aag 1 0 1 0 0 1 2 3 2 +b0 po0 diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig index 8d0ba13b1..6fcf62522 100644 --- a/tests/aiger/cnt1.aig +++ b/tests/aiger/cnt1.aig @@ -1,3 +1,4 @@ aig 1 0 1 0 0 1 3 2 +b0 po0 diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag index 6db3f0ffd..35cd5a482 100644 --- a/tests/aiger/cnt1e.aag +++ b/tests/aiger/cnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 po0 diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig index d8d159f11..7284dd42a 100644 --- a/tests/aiger/cnt1e.aig +++ b/tests/aiger/cnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 4 -b0 AIGER_NEVER +i0 po0 +b0 AIGER_NEVER diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag index 421e64a91..bab4a06a6 100644 --- a/tests/aiger/false.aag +++ b/tests/aiger/false.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 0 +o0 po0 diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig index ad7d039fa..4dc442d7b 100644 --- a/tests/aiger/false.aig +++ b/tests/aiger/false.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 0 +o0 po0 diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag index ff7c28542..428bad9e4 100644 --- a/tests/aiger/inverter.aag +++ b/tests/aiger/inverter.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 3 +i0 pi0 +o0 po0 diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig index 525d82392..5bec90ae3 100644 --- a/tests/aiger/inverter.aig +++ b/tests/aiger/inverter.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 3 +i0 pi0 +o0 po0 diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag index 141c864f7..2ed645d84 100644 --- a/tests/aiger/notcnt1e.aag +++ b/tests/aiger/notcnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 pi0 diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig index 7c85a7290..fd7e94508 100644 --- a/tests/aiger/notcnt1e.aig +++ b/tests/aiger/notcnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 5 -b0 AIGER_NEVER +i0 pi0 +b0 AIGER_NEVER diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig deleted file mode 100644 index 75c9e4480..000000000 --- a/tests/aiger/or.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -7 - \ No newline at end of file diff --git a/tests/aiger/or.aag b/tests/aiger/or_.aag similarity index 55% rename from tests/aiger/or.aag rename to tests/aiger/or_.aag index f780e339f..0f619dba3 100644 --- a/tests/aiger/or.aag +++ b/tests/aiger/or_.aag @@ -3,3 +3,6 @@ aag 3 2 0 1 1 4 7 6 3 5 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/or_.aig b/tests/aiger/or_.aig new file mode 100644 index 000000000..051687512 --- /dev/null +++ b/tests/aiger/or_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +7 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag index 09651012d..b1a1582d7 100644 --- a/tests/aiger/toggle.aag +++ b/tests/aiger/toggle.aag @@ -2,3 +2,5 @@ aag 1 0 1 2 0 2 3 2 3 +o0 po0 +o1 po1 diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig index b69e21aaf..68b41763f 100644 --- a/tests/aiger/toggle.aig +++ b/tests/aiger/toggle.aig @@ -2,3 +2,5 @@ aig 1 0 1 2 0 3 2 3 +o0 po0 +o1 po1 diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag index 366893648..66a9eab46 100644 --- a/tests/aiger/true.aag +++ b/tests/aiger/true.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 1 +o0 po0 diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig index 10086f389..f9bad6000 100644 --- a/tests/aiger/true.aig +++ b/tests/aiger/true.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 1 +o0 po0 From ebe29b66593414d0317879359d1f1d1f61a9ecc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:05:36 -0700 Subject: [PATCH 48/57] Use ABC to convert AIGER to Verilog, then sat against Yosys --- tests/aiger/run-test.sh | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index e0a34f023..70300d305 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -1,24 +1,18 @@ #!/bin/bash -OPTIND=1 -seed="" # default to no seed specified -while getopts "S:" opt -do - case "$opt" in - S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space - seed="SEED=$arg" ;; - esac +set -e +for aig in *.aig; do + ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" + ../../yosys -p " +read_verilog ${aig%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aig +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" done -shift "$((OPTIND-1))" - -# check for Icarus Verilog -if ! which iverilog > /dev/null ; then - echo "$0: Error: Icarus Verilog 'iverilog' not found." - exit 1 -fi - -echo "===== AAG ======" -${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" - -echo "===== AIG ======" -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger" From abc40924ed5dc4aba91c7f1e83ca90f54e9eb455 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:06:57 -0700 Subject: [PATCH 49/57] Use ABC to convert from AIGER to Verilog --- tests/tools/autotest.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 0a511f29c..23964a751 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -146,9 +146,10 @@ do rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} + elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then + "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v" else - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog -noblackbox" + cp ../${fn} ${bn}_ref.${ext} fi if [ ! -f ../${bn}_tb.v ]; then From a04521c6b70396a590f0ddb3081c4c5d6b01671e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:07:15 -0700 Subject: [PATCH 50/57] Fix read_aiger -- create zero driver, fix init width, parse 'b' --- frontends/aiger/aigerparse.cc | 64 ++++++++++++++++++++++++++++------- frontends/aiger/aigerparse.h | 1 + 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 38348cd65..26b101e4c 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -81,11 +81,26 @@ end_of_header: else log_abort(); + RTLIL::Wire* n0 = module->wire("\\n0"); + if (n0) + module->connect(n0, RTLIL::S0); + + for (unsigned i = 0; i < outputs.size(); ++i) { + RTLIL::Wire *wire = outputs[i]; + if (wire->port_input) { + RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o"); + o_wire->port_output = true; + wire->port_output = false; + module->connect(o_wire, wire); + outputs[i] = o_wire; + } + } + // Parse footer (symbol table, comments, etc.) unsigned l1; std::string s; for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) { - if (c == 'i' || c == 'l' || c == 'o') { + if (c == 'i' || c == 'l' || c == 'o' || c == 'b') { f.ignore(1); if (!(f >> l1 >> s)) log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); @@ -97,11 +112,12 @@ end_of_header: if (c == 'i') wire = inputs[l1]; else if (c == 'l') wire = latches[l1]; else if (c == 'o') wire = outputs[l1]; + else if (c == 'b') wire = bad_properties[l1]; else log_abort(); module->rename(wire, stringf("\\%s", s.c_str())); } - else if (c == 'b' || c == 'j' || c == 'f') { + else if (c == 'j' || c == 'f') { // TODO } else if (c == 'c') { @@ -153,7 +169,7 @@ void AigerReader::parse_aiger_ascii() unsigned l1, l2, l3; // Parse inputs - for (unsigned i = 0; i < I; ++i, ++line_count) { + for (unsigned i = 1; i <= I; ++i, ++line_count) { if (!(f >> l1)) log_error("Line %u cannot be interpreted as an input!\n", line_count); log_debug("%d is an input\n", l1); @@ -187,8 +203,10 @@ void AigerReader::parse_aiger_ascii() if (!(f >> l3)) log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0 || l3 == 1) - q_wire->attributes["\\init"] = RTLIL::Const(l3); + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; else if (l3 == l1) { //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); } @@ -197,7 +215,7 @@ void AigerReader::parse_aiger_ascii() } else { // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::Const(0); + q_wire->attributes["\\init"] = RTLIL::S0; } latches.push_back(q_wire); } @@ -214,8 +232,17 @@ void AigerReader::parse_aiger_ascii() } std::getline(f, line); // Ignore up to start of next line - // TODO: Parse bad state properties - for (unsigned i = 0; i < B; ++i, ++line_count) + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); + + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } + if (B > 0) std::getline(f, line); // Ignore up to start of next line // TODO: Parse invariant constraints @@ -290,8 +317,10 @@ void AigerReader::parse_aiger_binary() if (!(f >> l3)) log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0 || l3 == 1) - q_wire->attributes["\\init"] = RTLIL::Const(l3); + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; else if (l3 == l1) { //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); } @@ -300,7 +329,7 @@ void AigerReader::parse_aiger_binary() } else { // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::Const(0); + q_wire->attributes["\\init"] = RTLIL::S0; } latches.push_back(q_wire); } @@ -317,8 +346,17 @@ void AigerReader::parse_aiger_binary() } std::getline(f, line); // Ignore up to start of next line - // TODO: Parse bad state properties - for (unsigned i = 0; i < B; ++i, ++line_count) + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); + + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } + if (B > 0) std::getline(f, line); // Ignore up to start of next line // TODO: Parse invariant constraints diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index c49cd152d..0e3719cc4 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -39,6 +39,7 @@ struct AigerReader std::vector inputs; std::vector latches; std::vector outputs; + std::vector bad_properties; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name); void parse_aiger(); From 65924fd12f48b4ec5a4d51efeea977992d033ecf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:28:05 -0700 Subject: [PATCH 51/57] Test *.aag too, by using *.aig as reference --- tests/aiger/run-test.sh | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index 70300d305..e56d0fa80 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -1,6 +1,25 @@ #!/bin/bash set -e + +for aag in *.aag; do + # Since ABC cannot read *.aag, read the *.aig instead + # (which would have been created by the reference aig2aig utility) + ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" + ../../yosys -p " +read_verilog ${aag%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aag +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" +done + for aig in *.aig; do ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" ../../yosys -p " From d00ae1d6a8c0a1e147599ee27f6a4ea68f43267e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:28:25 -0700 Subject: [PATCH 52/57] Remove unnecessary std::getline() for ASCII --- frontends/aiger/aigerparse.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 26b101e4c..d0338e45d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -230,7 +230,6 @@ void AigerReader::parse_aiger_ascii() wire->port_output = true; outputs.push_back(wire); } - std::getline(f, line); // Ignore up to start of next line // Parse bad properties for (unsigned i = 0; i < B; ++i, ++line_count) { @@ -242,8 +241,6 @@ void AigerReader::parse_aiger_ascii() wire->port_output = true; bad_properties.push_back(wire); } - if (B > 0) - std::getline(f, line); // Ignore up to start of next line // TODO: Parse invariant constraints for (unsigned i = 0; i < C; ++i, ++line_count) From 6934f4bdd53cb226d0c8631eff691d9a96aebbce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:30:36 -0700 Subject: [PATCH 53/57] Fix spacing (entire file is wrong anyway, will fix later) --- frontends/aiger/aigerparse.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d0338e45d..32be4cf6c 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -81,9 +81,9 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire("\\n0"); - if (n0) - module->connect(n0, RTLIL::S0); + RTLIL::Wire* n0 = module->wire("\\n0"); + if (n0) + module->connect(n0, RTLIL::S0); for (unsigned i = 0; i < outputs.size(); ++i) { RTLIL::Wire *wire = outputs[i]; From f48c6920b7aa777c0c569f444e3db88211835cec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 13:12:48 -0700 Subject: [PATCH 54/57] Add read_aiger to CHANGELOG --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 36b64e111..839fefcf1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" From 2b350401c4577d54c0d460240e2d2847d2eeadc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 15:44:57 -0700 Subject: [PATCH 55/57] Fix spacing from spaces to tabs --- frontends/aiger/aigerparse.cc | 634 +++++++++++++++++----------------- 1 file changed, 317 insertions(+), 317 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 32be4cf6c..68552fd06 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -34,389 +34,389 @@ YOSYS_NAMESPACE_BEGIN AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name) - : design(design), f(f), clk_name(clk_name) + : design(design), f(f), clk_name(clk_name) { - module = new RTLIL::Module; - module->name = module_name; - if (design->module(module->name)) - log_error("Duplicate definition of module %s!\n", log_id(module->name)); + module = new RTLIL::Module; + module->name = module_name; + if (design->module(module->name)) + log_error("Duplicate definition of module %s!\n", log_id(module->name)); } void AigerReader::parse_aiger() { - std::string header; - f >> header; - if (header != "aag" && header != "aig") - log_error("Unsupported AIGER file!\n"); + std::string header; + f >> header; + if (header != "aag" && header != "aig") + log_error("Unsupported AIGER file!\n"); - // Parse rest of header - if (!(f >> M >> I >> L >> O >> A)) - log_error("Invalid AIGER header\n"); + // Parse rest of header + if (!(f >> M >> I >> L >> O >> A)) + log_error("Invalid AIGER header\n"); - // Optional values - B = C = J = F = 0; - if (f.peek() != ' ') goto end_of_header; - if (!(f >> B)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> C)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> J)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> F)) log_error("Invalid AIGER header\n"); + // Optional values + B = C = J = F = 0; + if (f.peek() != ' ') goto end_of_header; + if (!(f >> B)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> C)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> J)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> F)) log_error("Invalid AIGER header\n"); end_of_header: - std::string line; - std::getline(f, line); // Ignore up to start of next line, as standard - // says anything that follows could be used for - // optional sections + std::string line; + std::getline(f, line); // Ignore up to start of next line, as standard + // says anything that follows could be used for + // optional sections - log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F); + log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F); - line_count = 1; + line_count = 1; - if (header == "aag") - parse_aiger_ascii(); - else if (header == "aig") - parse_aiger_binary(); - else - log_abort(); + if (header == "aag") + parse_aiger_ascii(); + else if (header == "aig") + parse_aiger_binary(); + else + log_abort(); - RTLIL::Wire* n0 = module->wire("\\n0"); - if (n0) - module->connect(n0, RTLIL::S0); + RTLIL::Wire* n0 = module->wire("\\n0"); + if (n0) + module->connect(n0, RTLIL::S0); - for (unsigned i = 0; i < outputs.size(); ++i) { - RTLIL::Wire *wire = outputs[i]; - if (wire->port_input) { - RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o"); - o_wire->port_output = true; - wire->port_output = false; - module->connect(o_wire, wire); - outputs[i] = o_wire; - } - } + for (unsigned i = 0; i < outputs.size(); ++i) { + RTLIL::Wire *wire = outputs[i]; + if (wire->port_input) { + RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o"); + o_wire->port_output = true; + wire->port_output = false; + module->connect(o_wire, wire); + outputs[i] = o_wire; + } + } - // Parse footer (symbol table, comments, etc.) - unsigned l1; - std::string s; - for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) { - if (c == 'i' || c == 'l' || c == 'o' || c == 'b') { - f.ignore(1); - if (!(f >> l1 >> s)) - log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); + // Parse footer (symbol table, comments, etc.) + unsigned l1; + std::string s; + for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) { + if (c == 'i' || c == 'l' || c == 'o' || c == 'b') { + f.ignore(1); + if (!(f >> l1 >> s)) + log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); - if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) - log_error("Line %u has invalid symbol position!\n", line_count); + if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) + log_error("Line %u has invalid symbol position!\n", line_count); - RTLIL::Wire* wire; - if (c == 'i') wire = inputs[l1]; - else if (c == 'l') wire = latches[l1]; - else if (c == 'o') wire = outputs[l1]; - else if (c == 'b') wire = bad_properties[l1]; - else log_abort(); + RTLIL::Wire* wire; + if (c == 'i') wire = inputs[l1]; + else if (c == 'l') wire = latches[l1]; + else if (c == 'o') wire = outputs[l1]; + else if (c == 'b') wire = bad_properties[l1]; + else log_abort(); - module->rename(wire, stringf("\\%s", s.c_str())); - } - else if (c == 'j' || c == 'f') { - // TODO - } - else if (c == 'c') { - f.ignore(1); - if (f.peek() == '\n') - break; - // Else constraint (TODO) - } - else - log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); - std::getline(f, line); // Ignore up to start of next line - } + module->rename(wire, stringf("\\%s", s.c_str())); + } + else if (c == 'j' || c == 'f') { + // TODO + } + else if (c == 'c') { + f.ignore(1); + if (f.peek() == '\n') + break; + // Else constraint (TODO) + } + else + log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); + std::getline(f, line); // Ignore up to start of next line + } - module->fixup_ports(); - design->add(module); + module->fixup_ports(); + design->add(module); } static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal) { - const unsigned variable = literal >> 1; - const bool invert = literal & 1; - RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix? - RTLIL::Wire *wire = module->wire(wire_name); - if (wire) return wire; - log_debug("Creating %s\n", wire_name.c_str()); - wire = module->addWire(wire_name); - if (!invert) return wire; - RTLIL::IdString wire_inv_name(stringf("\\n%d", variable)); - RTLIL::Wire *wire_inv = module->wire(wire_inv_name); - if (wire_inv) { - if (module->cell(wire_inv_name)) return wire; - } - else { - log_debug("Creating %s\n", wire_inv_name.c_str()); - wire_inv = module->addWire(wire_inv_name); - } + const unsigned variable = literal >> 1; + const bool invert = literal & 1; + RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix? + RTLIL::Wire *wire = module->wire(wire_name); + if (wire) return wire; + log_debug("Creating %s\n", wire_name.c_str()); + wire = module->addWire(wire_name); + if (!invert) return wire; + RTLIL::IdString wire_inv_name(stringf("\\n%d", variable)); + RTLIL::Wire *wire_inv = module->wire(wire_inv_name); + if (wire_inv) { + if (module->cell(wire_inv_name)) return wire; + } + else { + log_debug("Creating %s\n", wire_inv_name.c_str()); + wire_inv = module->addWire(wire_inv_name); + } - log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); - module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix? + log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); + module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix? - return wire; + return wire; } void AigerReader::parse_aiger_ascii() { - std::string line; - std::stringstream ss; + std::string line; + std::stringstream ss; - unsigned l1, l2, l3; + unsigned l1, l2, l3; - // Parse inputs - for (unsigned i = 1; i <= I; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an input!\n", line_count); - log_debug("%d is an input\n", l1); - log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted? - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_input = true; - inputs.push_back(wire); - } + // Parse inputs + for (unsigned i = 1; i <= I; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an input!\n", line_count); + log_debug("%d is an input\n", l1); + log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted? + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_input = true; + inputs.push_back(wire); + } - // Parse latches - RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - clk_wire = module->wire(clk_name); - log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); - clk_wire->port_input = true; - } - for (unsigned i = 0; i < L; ++i, ++line_count) { - if (!(f >> l1 >> l2)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); - log_debug("%d %d is a latch\n", l1, l2); - log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted? - RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); + // Parse latches + RTLIL::Wire *clk_wire = nullptr; + if (L > 0) { + clk_wire = module->wire(clk_name); + log_assert(!clk_wire); + log_debug("Creating %s\n", clk_name.c_str()); + clk_wire = module->addWire(clk_name); + clk_wire->port_input = true; + } + for (unsigned i = 0; i < L; ++i, ++line_count) { + if (!(f >> l1 >> l2)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); + log_debug("%d %d is a latch\n", l1, l2); + log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted? + RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); - // Reset logic is optional in AIGER 1.9 - if (f.peek() == ' ') { - if (!(f >> l3)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); + // Reset logic is optional in AIGER 1.9 + if (f.peek() == ' ') { + if (!(f >> l3)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0) - q_wire->attributes["\\init"] = RTLIL::S0; - else if (l3 == 1) - q_wire->attributes["\\init"] = RTLIL::S1; - else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); - } - else - log_error("Line %u has invalid reset literal for latch!\n", line_count); - } - else { - // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::S0; - } - latches.push_back(q_wire); - } + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; + else if (l3 == l1) { + //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); + } + else + log_error("Line %u has invalid reset literal for latch!\n", line_count); + } + else { + // AIGER latches are assumed to be initialized to zero + q_wire->attributes["\\init"] = RTLIL::S0; + } + latches.push_back(q_wire); + } - // Parse outputs - for (unsigned i = 0; i < O; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an output!\n", line_count); + // Parse outputs + for (unsigned i = 0; i < O; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an output!\n", line_count); - log_debug("%d is an output\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - outputs.push_back(wire); - } + log_debug("%d is an output\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + outputs.push_back(wire); + } - // Parse bad properties - for (unsigned i = 0; i < B; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); - log_debug("%d is a bad state property\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - bad_properties.push_back(wire); - } + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } - // TODO: Parse invariant constraints - for (unsigned i = 0; i < C; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse invariant constraints + for (unsigned i = 0; i < C; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse justice properties - for (unsigned i = 0; i < J; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse justice properties + for (unsigned i = 0; i < J; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse fairness constraints - for (unsigned i = 0; i < F; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse fairness constraints + for (unsigned i = 0; i < F; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // Parse AND - for (unsigned i = 0; i < A; ++i) { - if (!(f >> l1 >> l2 >> l3)) - log_error("Line %u cannot be interpreted as an AND!\n", line_count); + // Parse AND + for (unsigned i = 0; i < A; ++i) { + if (!(f >> l1 >> l2 >> l3)) + log_error("Line %u cannot be interpreted as an AND!\n", line_count); - log_debug("%d %d %d is an AND\n", l1, l2, l3); - log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? - RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); - RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); - } - std::getline(f, line); // Ignore up to start of next line + log_debug("%d %d %d is an AND\n", l1, l2, l3); + log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? + RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); + RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); + module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); + } + std::getline(f, line); // Ignore up to start of next line } static unsigned parse_next_delta_literal(std::istream &f, unsigned ref) { - unsigned x = 0, i = 0; - unsigned char ch; - while ((ch = f.get()) & 0x80) - x |= (ch & 0x7f) << (7 * i++); - return ref - (x | (ch << (7 * i))); + unsigned x = 0, i = 0; + unsigned char ch; + while ((ch = f.get()) & 0x80) + x |= (ch & 0x7f) << (7 * i++); + return ref - (x | (ch << (7 * i))); } void AigerReader::parse_aiger_binary() { - unsigned l1, l2, l3; - std::string line; + unsigned l1, l2, l3; + std::string line; - // Parse inputs - for (unsigned i = 1; i <= I; ++i) { - RTLIL::Wire *wire = createWireIfNotExists(module, i << 1); - wire->port_input = true; - inputs.push_back(wire); - } + // Parse inputs + for (unsigned i = 1; i <= I; ++i) { + RTLIL::Wire *wire = createWireIfNotExists(module, i << 1); + wire->port_input = true; + inputs.push_back(wire); + } - // Parse latches - RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - clk_wire = module->wire(clk_name); - log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); - clk_wire->port_input = true; - } - l1 = (I+1) * 2; - for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) { - if (!(f >> l2)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); - log_debug("%d %d is a latch\n", l1, l2); - RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); + // Parse latches + RTLIL::Wire *clk_wire = nullptr; + if (L > 0) { + clk_wire = module->wire(clk_name); + log_assert(!clk_wire); + log_debug("Creating %s\n", clk_name.c_str()); + clk_wire = module->addWire(clk_name); + clk_wire->port_input = true; + } + l1 = (I+1) * 2; + for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) { + if (!(f >> l2)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); + log_debug("%d %d is a latch\n", l1, l2); + RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + module->addDff(NEW_ID, clk_wire, d_wire, q_wire); - // Reset logic is optional in AIGER 1.9 - if (f.peek() == ' ') { - if (!(f >> l3)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); + // Reset logic is optional in AIGER 1.9 + if (f.peek() == ' ') { + if (!(f >> l3)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0) - q_wire->attributes["\\init"] = RTLIL::S0; - else if (l3 == 1) - q_wire->attributes["\\init"] = RTLIL::S1; - else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); - } - else - log_error("Line %u has invalid reset literal for latch!\n", line_count); - } - else { - // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::S0; - } - latches.push_back(q_wire); - } + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; + else if (l3 == l1) { + //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); + } + else + log_error("Line %u has invalid reset literal for latch!\n", line_count); + } + else { + // AIGER latches are assumed to be initialized to zero + q_wire->attributes["\\init"] = RTLIL::S0; + } + latches.push_back(q_wire); + } - // Parse outputs - for (unsigned i = 0; i < O; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an output!\n", line_count); + // Parse outputs + for (unsigned i = 0; i < O; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an output!\n", line_count); - log_debug("%d is an output\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - outputs.push_back(wire); - } - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is an output\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + outputs.push_back(wire); + } + std::getline(f, line); // Ignore up to start of next line - // Parse bad properties - for (unsigned i = 0; i < B; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); - log_debug("%d is a bad state property\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - bad_properties.push_back(wire); - } - if (B > 0) - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } + if (B > 0) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse invariant constraints - for (unsigned i = 0; i < C; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse invariant constraints + for (unsigned i = 0; i < C; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse justice properties - for (unsigned i = 0; i < J; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse justice properties + for (unsigned i = 0; i < J; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse fairness constraints - for (unsigned i = 0; i < F; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse fairness constraints + for (unsigned i = 0; i < F; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // Parse AND - l1 = (I+L+1) << 1; - for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) { - l2 = parse_next_delta_literal(f, l1); - l3 = parse_next_delta_literal(f, l2); + // Parse AND + l1 = (I+L+1) << 1; + for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) { + l2 = parse_next_delta_literal(f, l1); + l3 = parse_next_delta_literal(f, l2); - log_debug("%d %d %d is an AND\n", l1, l2, l3); - log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? - RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); - RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); + log_debug("%d %d %d is an AND\n", l1, l2, l3); + log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? + RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); + RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_"); - and_cell->setPort("\\A", i1_wire); - and_cell->setPort("\\B", i2_wire); - and_cell->setPort("\\Y", o_wire); - } + RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_"); + and_cell->setPort("\\A", i1_wire); + and_cell->setPort("\\B", i2_wire); + and_cell->setPort("\\Y", o_wire); + } } struct AigerFrontend : public Frontend { - AigerFrontend() : Frontend("aiger", "read AIGER file") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" read_aiger [options] [filename]\n"); - log("\n"); - log("Load module from an AIGER file into the current design.\n"); - log("\n"); - log(" -module_name \n"); - log(" Name of module to be created (default: )" + AigerFrontend() : Frontend("aiger", "read AIGER file") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" read_aiger [options] [filename]\n"); + log("\n"); + log("Load module from an AIGER file into the current design.\n"); + log("\n"); + log(" -module_name \n"); + log(" Name of module to be created (default: " #ifdef _WIN32 - "top" // FIXME + "top" // FIXME #else - "" + "" #endif - ")\n"); - log("\n"); - log(" -clk_name \n"); - log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); - log(" this name (default: clk)\n"); - log("\n"); - } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing AIGER frontend.\n"); + ")\n"); + log("\n"); + log(" -clk_name \n"); + log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); + log(" this name (default: clk)\n"); + log("\n"); + } + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing AIGER frontend.\n"); - RTLIL::IdString clk_name = "\\clk"; - RTLIL::IdString module_name; + RTLIL::IdString clk_name = "\\clk"; + RTLIL::IdString module_name; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -433,19 +433,19 @@ struct AigerFrontend : public Frontend { } extra_args(f, filename, args, argidx); - if (module_name.empty()) { + if (module_name.empty()) { #ifdef _WIN32 - module_name = "top"; // FIXME: basename equivalent on Win32? + module_name = "top"; // FIXME: basename equivalent on Win32? #else - char* bn = strdup(filename.c_str()); - module_name = RTLIL::escape_id(bn); - free(bn); + char* bn = strdup(filename.c_str()); + module_name = RTLIL::escape_id(bn); + free(bn); #endif - } + } - AigerReader reader(design, *f, module_name, clk_name); + AigerReader reader(design, *f, module_name, clk_name); reader.parse_aiger(); - } + } } AigerFrontend; YOSYS_NAMESPACE_END From abf90b040331f9fd48c9e4bdb4bbb952db4c2d04 Mon Sep 17 00:00:00 2001 From: Simon Schubert <2@0x2c.org> Date: Mon, 10 Jun 2019 11:49:08 +0200 Subject: [PATCH 56/57] ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k --- techlibs/ice40/cells_sim.v | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index e89405b22..f9945b2b5 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -973,6 +973,30 @@ parameter RGB1_CURRENT = "0b000000"; parameter RGB2_CURRENT = "0b000000"; endmodule +(* blackbox *) +module SB_LED_DRV_CUR( + input EN, + output LEDPU +); +endmodule + +(* blackbox *) +module SB_RGB_DRV( + input RGBLEDEN, + input RGB0PWM, + input RGB1PWM, + input RGB2PWM, + input RGBPU, + output RGB0, + output RGB1, + output RGB2 +); +parameter CURRENT_MODE = "0b0"; +parameter RGB0_CURRENT = "0b000000"; +parameter RGB1_CURRENT = "0b000000"; +parameter RGB2_CURRENT = "0b000000"; +endmodule + (* blackbox *) module SB_I2C( input SBCLKI, From a91ea6612a73568782c80bd12ce2875353e2b5c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 10:27:55 -0700 Subject: [PATCH 57/57] Add some more comments --- tests/aiger/run-test.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index e56d0fa80..f52eb4ac1 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -2,9 +2,14 @@ set -e +# NB: *.aag and *.aig must contain a symbol table naming the primary +# inputs and outputs, otherwise ABC and Yosys will name them +# arbitrarily (and inconsistently with each other). + for aag in *.aag; do # Since ABC cannot read *.aag, read the *.aig instead - # (which would have been created by the reference aig2aig utility) + # (which would have been created by the reference aig2aig utility, + # available from http://fmv.jku.at/aiger/) ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" ../../yosys -p " read_verilog ${aag%.*}_ref.v