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tests: add testcase for clean-ing unused (* init *)
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@ -11,3 +11,32 @@ EOT
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clean
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select -assert-count 1 a:init
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select -assert-count 1 w:y a:init %i
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design -reset
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read_verilog <<EOT
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module top(input clk, d, output q);
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(* init=1'b0 *) wire private0;
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reg private1 = 1'b1;
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always @(posedge clk)
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private1 <= d;
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assign q = private1;
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endmodule
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EOT
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proc
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rename -hide w:private*
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clean
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select -assert-count 1 a:init=1'b1
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select -assert-count 0 a:init=1'b0
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design -reset
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read_verilog <<EOT
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module top;
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(* init=1'b0 *) wire private;
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wire public = private;
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endmodule
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EOT
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rename -hide w:private
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clean
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select -assert-none w:*
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