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Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
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Andrew Zonenberg
parent
007f29b9c2
commit
fe3a932cfa
4 changed files with 451 additions and 428 deletions
357
techlibs/greenpak4/cells_sim_digital.v
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357
techlibs/greenpak4/cells_sim_digital.v
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`timescale 1ns/1ps
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/*
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This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
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behavioral Verilog constructs only.
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*/
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_CLKBUF(input wire IN, output wire OUT);
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assign OUT = IN;
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endmodule
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module GP_DCMPREF(output reg[7:0]OUT);
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parameter[7:0] REF_VAL = 8'h00;
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initial OUT = REF_VAL;
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endmodule
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module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
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always @(*) begin
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case(SEL)
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2'd00: begin
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OUTA <= IN0;
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OUTB <= IN3;
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end
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2'd01: begin
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OUTA <= IN1;
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OUTB <= IN2;
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end
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2'd02: begin
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OUTA <= IN2;
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OUTB <= IN1;
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end
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2'd03: begin
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OUTA <= IN3;
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OUTB <= IN0;
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end
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endcase
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end
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endmodule
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module GP_DELAY(input IN, output reg OUT);
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parameter DELAY_STEPS = 1;
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parameter GLITCH_FILTER = 0;
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initial OUT = 0;
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generate
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if(GLITCH_FILTER) begin
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initial begin
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$display("ERROR: GP_DELAY glitch filter mode not implemented");
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$finish;
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end
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end
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//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
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//Change simulation-mode delay depending on global Vdd range (how to specify this?)
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always @(*) begin
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case(DELAY_STEPS)
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1: #166 OUT = IN;
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2: #318 OUT = IN;
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2: #471 OUT = IN;
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3: #622 OUT = IN;
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default: begin
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$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
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$finish;
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end
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endcase
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end
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endgenerate
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endmodule
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module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFI(input D, CLK, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK) begin
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nQ <= ~D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFRI(input D, CLK, nRST, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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nQ <= 1'b1;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSI(input D, CLK, nSET, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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nQ <= 1'b0;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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nQ <= ~SRMODE;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCH(input D, input nCLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHI(input D, input nCLK, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nRST)
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Q <= 1'b0;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nRST)
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nQ <= 1'b1;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nSET)
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Q <= 1'b1;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nSET)
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nQ <= 1'b0;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter[0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nSR)
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Q <= SRMODE;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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parameter[0:0] SRMODE = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nSR)
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nQ <= ~SRMODE;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_IBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_IOBUF(input IN, input OE, output OUT, inout IO);
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assign OUT = IO;
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assign IO = OE ? IN : 1'bz;
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endmodule
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module GP_INV(input IN, output OUT);
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assign OUT = ~IN;
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endmodule
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module GP_OBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_OBUFT(input IN, input OE, output OUT);
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assign OUT = OE ? IN : 1'bz;
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endmodule
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module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
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initial OUT = 0;
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parameter PATTERN_DATA = 16'h0;
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parameter PATTERN_LEN = 5'd16;
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reg[3:0] count = 0;
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always @(posedge CLK) begin
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if(!nRST)
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OUT <= PATTERN_DATA[0];
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else begin
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count <= count + 1;
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OUT <= PATTERN_DATA[count];
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if( (count + 1) == PATTERN_LEN)
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count <= 0;
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end
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end
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endmodule
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module GP_POR(output reg RST_DONE);
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parameter POR_TIME = 500;
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initial begin
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RST_DONE = 0;
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if(POR_TIME == 4)
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#4000;
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else if(POR_TIME == 500)
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#500000;
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else begin
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$display("ERROR: bad POR_TIME for GP_POR cell");
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$finish;
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end
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RST_DONE = 1;
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end
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endmodule
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module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
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parameter OUTA_TAP = 1;
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parameter OUTA_INVERT = 0;
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parameter OUTB_TAP = 1;
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reg[15:0] shreg = 0;
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always @(posedge CLK, negedge nRST) begin
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if(!nRST)
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shreg = 0;
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else
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shreg <= {shreg[14:0], IN};
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end
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assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
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assign OUTB = shreg[OUTB_TAP - 1];
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endmodule
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module GP_VDD(output OUT);
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assign OUT = 1;
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endmodule
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module GP_VSS(output OUT);
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assign OUT = 0;
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endmodule
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