Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff

frontends/aiger/aigerparse.cc

@@ -432,7 +432,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 			else if (c == 'r') {
 				uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
 				flopNum = parse_xaiger_literal(f);
-				log_debug("flopNum: %u\n", flopNum);
+				log_debug("flopNum = %u\n", flopNum);
 				log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
 				f.ignore(flopNum * sizeof(uint32_t));
 			}
@@ -464,9 +464,10 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 					boxes.emplace_back(cell);
 				}
 			}
-			else if (c == 'a' || c == 'i' || c == 'o') {
+			else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
 				uint32_t dataSize = parse_xaiger_literal(f);
 				f.ignore(dataSize);
+				log_debug("ignoring '%c'\n", c);
 			}
 			else {
 				break;

passes/techmap/abc9.cc

@@ -1108,8 +1108,8 @@ struct Abc9Pass : public Pass {
 			std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
 			std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
 
-			typedef std::pair<IdString, SigSpec> endomain_t;
+			typedef std::pair<IdString, SigSpec> ctrldomain_t;
-			std::map<endomain_t, int> mergeability_class;
+			std::map<ctrldomain_t, int> mergeability_class;
 
 			for (auto cell : all_cells) {
 				for (auto &conn : cell->connections())
@@ -1149,7 +1149,7 @@ struct Abc9Pass : public Pass {
 				assigned_cells[abc9_clock].insert(cell->name);
 				assigned_cells_reverse[cell] = abc9_clock;
 
-				endomain_t key(cell->type, abc9_control);
+				ctrldomain_t key(cell->type, abc9_control);
 				auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
 				auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability),  r.first->second));
 				log_assert(r2.second);

techlibs/xilinx/abc9_map.v

@@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire $nextQ;
   FDRE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
@@ -209,7 +209,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
@@ -230,10 +230,10 @@ module FDSE (output reg Q, input C, CE, D, S);
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   wire $nextQ;
   FDSE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );

techlibs/xilinx/abc9_model.v

@@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
 (* abc_box_id = 1000 *)
 module \$__ABC9_ASYNC (input A, S, output Y);
 endmodule

tests/simple_abc9/abc9.v

@@ -268,13 +268,18 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk, d, r, output reg q);
+module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+always @(posedge clk1) q1 <= d;
+always @(negedge clk2) q2 <= q1;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
 always @(posedge clk or posedge r)
     if (r) q <= 1'b0;
     else q <= d;
 endmodule
 
-module abc9_test030(input clk, d, r, output reg q);
+module abc9_test031(input clk, d, r, output reg q);
 always @(negedge clk or posedge r)
     if (r) q <= 1'b1;
     else q <= d;

tests/various/abc9.v

@@ -10,7 +10,7 @@ unknown u(~i, w);
 unknown2 u2(w, o);
 endmodule
 
-module abc9_test031(input clk, d, r, output reg q);
+module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)
     if (r) q <= 1'b0;

tests/various/abc9.ys

@@ -24,7 +24,7 @@ select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
 
 design -load read
-hierarchy -top abc9_test031
+hierarchy -top abc9_test032
 proc
 clk2fflogic
 design -save gold