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rtlil: add roundtrip test for design -stash and design -save, fix #5321

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Emil J. Tywoniak 2025-09-02 19:56:28 +02:00
parent 4215f3c134
commit fdbdd193c1
3 changed files with 12 additions and 3 deletions
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tests/rtlil/roundtrip-design.sh Normal file
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set -euo pipefail
YS=../../yosys
$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il"
diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il
$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il"
diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il