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kernel: use more ID::*
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parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -72,11 +72,11 @@ struct Ice40FfssrPass : public Pass {
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if (cell->type != "$_MUX_")
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continue;
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SigBit bit_a = sigmap(cell->getPort("\\A"));
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SigBit bit_b = sigmap(cell->getPort("\\B"));
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SigBit bit_a = sigmap(cell->getPort(ID::A));
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SigBit bit_b = sigmap(cell->getPort(ID::B));
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if (bit_a.wire == nullptr || bit_b.wire == nullptr)
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sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
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sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
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}
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for (auto cell : ff_cells)
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@ -95,9 +95,9 @@ struct Ice40FfssrPass : public Pass {
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continue;
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Cell *mux_cell = sr_muxes.at(bit_d);
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SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
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SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
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SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
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SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
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SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
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SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
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log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
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log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
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@ -116,7 +116,7 @@ struct Ice40FfssrPass : public Pass {
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if (sr_val == State::S1) {
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cell->type = cell->type.str() + "SS";
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cell->setPort("\\S", sr_sig);
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cell->setPort(ID::S, sr_sig);
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cell->setPort("\\D", bit_d);
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} else {
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cell->type = cell->type.str() + "SR";
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