mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 14:53:42 +00:00
Code Activity

kernel: use more ID::*

Browse source
This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/ice40/ice40_ffinit.cc
View file

@ -133,13 +133,13 @@ struct Ice40FfinitPass : public Pass {
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
cell->setPort("\\R", cell->getPort("\\S"));
cell->unsetPort("\\S");
cell->setPort("\\R", cell->getPort(ID::S));
cell->unsetPort(ID::S);
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
cell->setPort("\\S", cell->getPort("\\R"));
cell->setPort(ID::S, cell->getPort("\\R"));
cell->unsetPort("\\R");
}

14
techlibs/ice40/ice40_ffssr.cc
View file

@ -72,11 +72,11 @@ struct Ice40FfssrPass : public Pass {
if (cell->type != "$_MUX_")
continue;
SigBit bit_a = sigmap(cell->getPort("\\A"));
SigBit bit_b = sigmap(cell->getPort("\\B"));
SigBit bit_a = sigmap(cell->getPort(ID::A));
SigBit bit_b = sigmap(cell->getPort(ID::B));
if (bit_a.wire == nullptr || bit_b.wire == nullptr)
sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
}
for (auto cell : ff_cells)
@ -95,9 +95,9 @@ struct Ice40FfssrPass : public Pass {
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
@ -116,7 +116,7 @@ struct Ice40FfssrPass : public Pass {
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
cell->setPort("\\S", sr_sig);
cell->setPort(ID::S, sr_sig);
cell->setPort("\\D", bit_d);
} else {
cell->type = cell->type.str() + "SR";

14
techlibs/ice40/ice40_opt.cc
View file

@ -95,8 +95,8 @@ static void run_ice40_opts(Module *module)
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
cell->getPort("\\A"),
cell->getPort("\\B"),
cell->getPort(ID::A),
cell->getPort(ID::B),
cell->getPort("\\CI")
};
for (int i = 0; i < 3; i++)
@ -140,9 +140,9 @@ static void run_ice40_opts(Module *module)
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort(ID::Y, cell->getPort("\\O"));
cell->unsetPort(ID::B);
cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
@ -182,13 +182,13 @@ static void run_ice40_opts(Module *module)
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({
cell->setPort(ID::A, SigSpec({
get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
}));
cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->setPort(ID::Y, cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");