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https://github.com/YosysHQ/yosys
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kernel: use more ID::*
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parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -44,14 +44,14 @@ struct proc_dlatch_db_t
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{
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if (cell->type.in("$mux", "$pmux"))
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{
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auto sig_y = sigmap(cell->getPort("\\Y"));
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auto sig_y = sigmap(cell->getPort(ID::Y));
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for (int i = 0; i < GetSize(sig_y); i++)
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mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
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pool<SigBit> mux_srcbits_pool;
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for (auto bit : sigmap(cell->getPort("\\A")))
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for (auto bit : sigmap(cell->getPort(ID::A)))
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mux_srcbits_pool.insert(bit);
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for (auto bit : sigmap(cell->getPort("\\B")))
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for (auto bit : sigmap(cell->getPort(ID::B)))
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mux_srcbits_pool.insert(bit);
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vector<SigBit> mux_srcbits_vec;
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@ -180,9 +180,9 @@ struct proc_dlatch_db_t
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Cell *cell = it->second.first;
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int index = it->second.second;
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SigSpec sig_a = sigmap(cell->getPort("\\A"));
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SigSpec sig_b = sigmap(cell->getPort("\\B"));
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SigSpec sig_s = sigmap(cell->getPort("\\S"));
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SigSpec sig_a = sigmap(cell->getPort(ID::A));
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SigSpec sig_b = sigmap(cell->getPort(ID::B));
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SigSpec sig_s = sigmap(cell->getPort(ID::S));
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int width = GetSize(sig_a);
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pool<int> children;
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@ -190,9 +190,9 @@ struct proc_dlatch_db_t
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int n = find_mux_feedback(sig_a[index], needle, set_undef);
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if (n != false_node) {
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if (set_undef && sig_a[index] == needle) {
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SigSpec sig = cell->getPort("\\A");
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SigSpec sig = cell->getPort(ID::A);
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sig[index] = State::Sx;
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cell->setPort("\\A", sig);
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cell->setPort(ID::A, sig);
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}
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for (int i = 0; i < GetSize(sig_s); i++)
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n = make_inner(sig_s[i], State::S0, n);
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@ -203,9 +203,9 @@ struct proc_dlatch_db_t
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n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
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if (n != false_node) {
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if (set_undef && sig_b[i*width + index] == needle) {
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SigSpec sig = cell->getPort("\\B");
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SigSpec sig = cell->getPort(ID::B);
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sig[i*width + index] = State::Sx;
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cell->setPort("\\B", sig);
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cell->setPort(ID::B, sig);
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}
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children.insert(make_inner(sig_s[i], State::S1, n));
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}
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@ -257,9 +257,9 @@ struct proc_dlatch_db_t
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void fixup_mux(Cell *cell)
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{
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SigSpec sig_a = cell->getPort("\\A");
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SigSpec sig_b = cell->getPort("\\B");
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SigSpec sig_s = cell->getPort("\\S");
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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SigSpec sig_s = cell->getPort(ID::S);
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SigSpec sig_any_valid_b;
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SigSpec sig_new_b, sig_new_s;
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@ -278,7 +278,7 @@ struct proc_dlatch_db_t
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}
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if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
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cell->setPort("\\A", sig_any_valid_b);
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cell->setPort(ID::A, sig_any_valid_b);
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if (GetSize(sig_new_s) == 1) {
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cell->type = "$mux";
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@ -288,8 +288,8 @@ struct proc_dlatch_db_t
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cell->setParam("\\S_WIDTH", GetSize(sig_new_s));
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}
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cell->setPort("\\B", sig_new_b);
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cell->setPort("\\S", sig_new_s);
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cell->setPort(ID::B, sig_new_b);
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cell->setPort(ID::S, sig_new_s);
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}
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void fixup_muxes()
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