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kernel: use more ID::*

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This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
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44
passes/proc/proc_arst.cc
View file

@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
if (cell->type == "$not" && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (!cell->getPort("\\A").as_bool())
if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
if (cell->getPort("\\B").is_fully_const()) {
if (!cell->getPort("\\B").as_bool())
if (cell->getPort(ID::B).is_fully_const()) {
if (!cell->getPort(ID::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) {
if (cell->getPort("\\A").as_bool())
if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort("\\B"), ref, polarity);
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
if (cell->getPort("\\B").is_fully_const()) {
if (cell->getPort("\\B").as_bool())
if (cell->getPort(ID::B).is_fully_const()) {
if (cell->getPort(ID::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort("\\A"), ref, polarity);
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
}

60
passes/proc/proc_dff.cc
View file

@ -79,8 +79,8 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->setPort("\\A", sync_low_signals);
cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
}
if (sync_low_signals.size() > 0) {
@ -88,9 +88,9 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->setPort("\\A", sync_low_signals);
cell->setPort("\\Y", mod->addWire(NEW_ID));
sync_high_signals.append(cell->getPort("\\Y"));
cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, mod->addWire(NEW_ID));
sync_high_signals.append(cell->getPort(ID::Y));
}
if (sync_high_signals.size() > 1) {
@ -98,30 +98,30 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->setPort("\\A", sync_high_signals);
cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
cell->setPort(ID::A, sync_high_signals);
cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
}
RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->setPort("\\A", sync_value);
inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
inv_cell->setPort(ID::A, sync_value);
inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_set_cell->setPort("\\A", sig_sr_set);
mux_set_cell->setPort("\\B", sync_value);
mux_set_cell->setPort("\\S", sync_high_signals);
mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
mux_set_cell->setPort(ID::A, sig_sr_set);
mux_set_cell->setPort(ID::B, sync_value);
mux_set_cell->setPort(ID::S, sync_high_signals);
mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_clr_cell->setPort("\\A", sig_sr_clr);
mux_clr_cell->setPort("\\B", sync_value_inv);
mux_clr_cell->setPort("\\S", sync_high_signals);
mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
mux_clr_cell->setPort(ID::A, sig_sr_clr);
mux_clr_cell->setPort(ID::B, sync_value_inv);
mux_clr_cell->setPort(ID::S, sync_high_signals);
mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
}
std::stringstream sstr;
@ -157,22 +157,22 @@ void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->setPort("\\A", sig_set);
inv_set->setPort("\\Y", sig_set_inv);
inv_set->setPort(ID::A, sig_set);
inv_set->setPort(ID::Y, sig_set_inv);
RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
mux_sr_set->setPort("\\Y", sig_sr_set);
mux_sr_set->setPort("\\S", set);
mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
mux_sr_set->setPort(ID::Y, sig_sr_set);
mux_sr_set->setPort(ID::S, set);
RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
mux_sr_clr->setPort("\\Y", sig_sr_clr);
mux_sr_clr->setPort("\\S", set);
mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
mux_sr_clr->setPort(ID::Y, sig_sr_clr);
mux_sr_clr->setPort(ID::S, set);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
@ -309,9 +309,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->setPort("\\A", inputs);
cell->setPort("\\B", compare);
cell->setPort("\\Y", sync_level->signal);
cell->setPort(ID::A, inputs);
cell->setPort(ID::B, compare);
cell->setPort(ID::Y, sync_level->signal);
many_async_rules.clear();
}

32
passes/proc/proc_dlatch.cc
View file

@ -44,14 +44,14 @@ struct proc_dlatch_db_t
{
if (cell->type.in("$mux", "$pmux"))
{
auto sig_y = sigmap(cell->getPort("\\Y"));
auto sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++)
mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
pool<SigBit> mux_srcbits_pool;
for (auto bit : sigmap(cell->getPort("\\A")))
for (auto bit : sigmap(cell->getPort(ID::A)))
mux_srcbits_pool.insert(bit);
for (auto bit : sigmap(cell->getPort("\\B")))
for (auto bit : sigmap(cell->getPort(ID::B)))
mux_srcbits_pool.insert(bit);
vector<SigBit> mux_srcbits_vec;
@ -180,9 +180,9 @@ struct proc_dlatch_db_t
Cell *cell = it->second.first;
int index = it->second.second;
SigSpec sig_a = sigmap(cell->getPort("\\A"));
SigSpec sig_b = sigmap(cell->getPort("\\B"));
SigSpec sig_s = sigmap(cell->getPort("\\S"));
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
int width = GetSize(sig_a);
pool<int> children;
@ -190,9 +190,9 @@ struct proc_dlatch_db_t
int n = find_mux_feedback(sig_a[index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_a[index] == needle) {
SigSpec sig = cell->getPort("\\A");
SigSpec sig = cell->getPort(ID::A);
sig[index] = State::Sx;
cell->setPort("\\A", sig);
cell->setPort(ID::A, sig);
}
for (int i = 0; i < GetSize(sig_s); i++)
n = make_inner(sig_s[i], State::S0, n);
@ -203,9 +203,9 @@ struct proc_dlatch_db_t
n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == needle) {
SigSpec sig = cell->getPort("\\B");
SigSpec sig = cell->getPort(ID::B);
sig[i*width + index] = State::Sx;
cell->setPort("\\B", sig);
cell->setPort(ID::B, sig);
}
children.insert(make_inner(sig_s[i], State::S1, n));
}
@ -257,9 +257,9 @@ struct proc_dlatch_db_t
void fixup_mux(Cell *cell)
{
SigSpec sig_a = cell->getPort("\\A");
SigSpec sig_b = cell->getPort("\\B");
SigSpec sig_s = cell->getPort("\\S");
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_s = cell->getPort(ID::S);
SigSpec sig_any_valid_b;
SigSpec sig_new_b, sig_new_s;
@ -278,7 +278,7 @@ struct proc_dlatch_db_t
}
if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
cell->setPort("\\A", sig_any_valid_b);
cell->setPort(ID::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
cell->type = "$mux";
@ -288,8 +288,8 @@ struct proc_dlatch_db_t
cell->setParam("\\S_WIDTH", GetSize(sig_new_s));
}
cell->setPort("\\B", sig_new_b);
cell->setPort("\\S", sig_new_s);
cell->setPort(ID::B, sig_new_b);
cell->setPort(ID::S, sig_new_s);
}
void fixup_muxes()

38
passes/proc/proc_mux.cc
View file

@ -147,7 +147,7 @@ struct SnippetSwCache
void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
{
cell->attributes = sw->attributes;
cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src));
}
RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
@ -188,9 +188,9 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
eq_cell->setPort("\\A", sig);
eq_cell->setPort("\\B", comp);
eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
eq_cell->setPort(ID::A, sig);
eq_cell->setPort(ID::B, comp);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
@ -211,8 +211,8 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
any_cell->setPort("\\A", cmp_wire);
any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire));
any_cell->setPort(ID::A, cmp_wire);
any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
@ -243,10 +243,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
mux_cell->setPort("\\A", else_signal);
mux_cell->setPort("\\B", when_signal);
mux_cell->setPort("\\S", ctrl_sig);
mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire));
mux_cell->setPort(ID::A, else_signal);
mux_cell->setPort(ID::B, when_signal);
mux_cell->setPort(ID::S, ctrl_sig);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
if (when_signal == last_mux_cell->getPort("\\A"))
if (when_signal == last_mux_cell->getPort(ID::A))
return;
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux";
RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S");
RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
new_s.append(ctrl_sig);
last_mux_cell->setPort("\\S", new_s);
last_mux_cell->setPort(ID::S, new_s);
RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B");
RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
new_b.append(when_signal);
last_mux_cell->setPort("\\B", new_b);
last_mux_cell->setPort(ID::B, new_b);
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort(ID::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
@ -281,7 +281,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul
{
pool<SigBit> bits;
if (sw->get_bool_attribute("\\full_case"))
if (sw->get_bool_attribute(ID::full_case))
{
bool first_case = true;
@ -337,7 +337,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
std::vector<int> pgroups(sw->cases.size());
bool is_simple_parallel_case = true;
if (!sw->get_bool_attribute("\\parallel_case")) {
if (!sw->get_bool_attribute(ID::parallel_case)) {
if (!swpara.count(sw)) {
pool<Const> case_values;
for (size_t i = 0; i < sw->cases.size(); i++) {

2
passes/proc/proc_prune.cc
View file

@ -38,7 +38,7 @@ struct PruneWorker
pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected)
{
pool<RTLIL::SigBit> all_assigned;
bool full_case = sw->get_bool_attribute("\\full_case");
bool full_case = sw->get_bool_attribute(ID::full_case);
bool first = true;
for (auto it : sw->cases) {
if (it->compare.empty())

4
passes/proc/proc_rmdead.cc
View file

@ -62,8 +62,8 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter)
pool.take_all();
}
if (pool.empty() && !sw->get_bool_attribute("\\full_case")) {
sw->set_bool_attribute("\\full_case");
if (pool.empty() && !sw->get_bool_attribute(ID::full_case)) {
sw->set_bool_attribute(ID::full_case);
full_case_counter++;
}
}