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kernel: use more ID::*
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parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -55,7 +55,7 @@ ret_false:
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list)
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{
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") {
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) {
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goto ret_false;
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}
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@ -67,8 +67,8 @@ ret_false:
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recursion_monitor.insert(cellport.first);
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RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
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RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
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if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
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recursion_monitor.erase(cellport.first);
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@ -99,18 +99,18 @@ static bool check_state_users(RTLIL::SigSpec sig)
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RTLIL::Cell *cell = cellport.first;
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if (muxtree_cells.count(cell) > 0)
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continue;
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if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig)
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if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig)
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continue;
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if (cellport.second != "\\A" && cellport.second != "\\B")
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if (cellport.second != ID::A && cellport.second != ID::B)
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return false;
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if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
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if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y))
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return false;
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for (auto &port_it : cell->connections())
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if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
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if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
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return false;
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if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
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if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
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continue;
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if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
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if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
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continue;
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return false;
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}
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@ -120,8 +120,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
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static void detect_fsm(RTLIL::Wire *wire)
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{
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bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none";
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bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none";
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bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
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bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
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bool has_init_attr = wire->attributes.count("\\init") > 0;
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bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
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bool looks_like_state_reg = false, looks_like_good_state_reg = false;
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@ -133,7 +133,7 @@ static void detect_fsm(RTLIL::Wire *wire)
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if (wire->width <= 1) {
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if (has_fsm_encoding_attr) {
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log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
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wire->attributes.erase("\\fsm_encoding");
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wire->attributes.erase(ID::fsm_encoding);
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}
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return;
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}
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@ -234,7 +234,7 @@ static void detect_fsm(RTLIL::Wire *wire)
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if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
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{
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log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
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wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
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wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
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}
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else
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if (looks_like_state_reg)
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