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kernel: use more ID::*

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This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
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26
passes/fsm/fsm_detect.cc
View file

@ -55,7 +55,7 @@ ret_false:
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list)
{
if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") {
if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) {
goto ret_false;
}
@ -67,8 +67,8 @@ ret_false:
recursion_monitor.insert(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
@ -99,18 +99,18 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig)
if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig)
continue;
if (cellport.second != "\\A" && cellport.second != "\\B")
if (cellport.second != ID::A && cellport.second != ID::B)
return false;
if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y))
return false;
for (auto &port_it : cell->connections())
if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
return false;
if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
continue;
if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
continue;
return false;
}
@ -120,8 +120,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
static void detect_fsm(RTLIL::Wire *wire)
{
bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none";
bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none";
bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
bool has_init_attr = wire->attributes.count("\\init") > 0;
bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
bool looks_like_state_reg = false, looks_like_good_state_reg = false;
@ -133,7 +133,7 @@ static void detect_fsm(RTLIL::Wire *wire)
if (wire->width <= 1) {
if (has_fsm_encoding_attr) {
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
wire->attributes.erase("\\fsm_encoding");
wire->attributes.erase(ID::fsm_encoding);
}
return;
}
@ -234,7 +234,7 @@ static void detect_fsm(RTLIL::Wire *wire)
if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
{
log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
}
else
if (looks_like_state_reg)

38
passes/fsm/fsm_expand.cc
View file

@ -51,32 +51,32 @@ struct FsmExpand
return true;
if (cell->type.in("$mux", "$pmux"))
if (cell->getPort("\\A").size() < 2)
if (cell->getPort(ID::A).size() < 2)
return true;
int in_bits = 0;
RTLIL::SigSpec new_signals;
if (cell->hasPort("\\A")) {
in_bits += GetSize(cell->getPort("\\A"));
new_signals.append(assign_map(cell->getPort("\\A")));
if (cell->hasPort(ID::A)) {
in_bits += GetSize(cell->getPort(ID::A));
new_signals.append(assign_map(cell->getPort(ID::A)));
}
if (cell->hasPort("\\B")) {
in_bits += GetSize(cell->getPort("\\B"));
new_signals.append(assign_map(cell->getPort("\\B")));
if (cell->hasPort(ID::B)) {
in_bits += GetSize(cell->getPort(ID::B));
new_signals.append(assign_map(cell->getPort(ID::B)));
}
if (cell->hasPort("\\S")) {
in_bits += GetSize(cell->getPort("\\S"));
new_signals.append(assign_map(cell->getPort("\\S")));
if (cell->hasPort(ID::S)) {
in_bits += GetSize(cell->getPort(ID::S));
new_signals.append(assign_map(cell->getPort(ID::S)));
}
if (in_bits > 8)
return false;
if (cell->hasPort("\\Y"))
new_signals.append(assign_map(cell->getPort("\\Y")));
if (cell->hasPort(ID::Y))
new_signals.append(assign_map(cell->getPort(ID::Y)));
new_signals.sort_and_unify();
new_signals.remove_const();
@ -106,7 +106,7 @@ struct FsmExpand
if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0)
continue;
for (auto &p : c->connections()) {
if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y")
if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y)
goto next_cell;
}
if (!is_cell_merge_candidate(c)) {
@ -159,12 +159,12 @@ struct FsmExpand
for (int i = 0; i < (1 << input_sig.size()); i++) {
RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
if (cell->hasPort("\\A"))
A = assign_map(cell->getPort("\\A"));
if (cell->hasPort("\\B"))
B = assign_map(cell->getPort("\\B"));
if (cell->hasPort("\\S"))
S = assign_map(cell->getPort("\\S"));
if (cell->hasPort(ID::A))
A = assign_map(cell->getPort(ID::A));
if (cell->hasPort(ID::B))
B = assign_map(cell->getPort(ID::B));
if (cell->hasPort(ID::S))
S = assign_map(cell->getPort(ID::S));
A.replace(input_sig, RTLIL::SigSpec(in_val));
B.replace(input_sig, RTLIL::SigSpec(in_val));
S.replace(input_sig, RTLIL::SigSpec(in_val));

32
passes/fsm/fsm_extract.cc
View file

@ -70,15 +70,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") {
if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
}
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_aa = sig;
sig_aa.replace(sig_y, sig_a);
@ -320,14 +320,14 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b;
if (cell->hasPort("\\B"))
sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (cellport.second == "\\A" && !sig_b.is_fully_const())
if (cell->hasPort(ID::B))
sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
if (cellport.second == ID::A && !sig_b.is_fully_const())
continue;
if (cellport.second == "\\B" && !sig_a.is_fully_const())
if (cellport.second == ID::B && !sig_a.is_fully_const())
continue;
log(" found ctrl output: %s\n", log_signal(sig_y));
ctrl_out.append(sig_y);
@ -382,7 +382,7 @@ static void extract_fsm(RTLIL::Wire *wire)
// rename original state wire
module->wires_.erase(wire->name);
wire->attributes.erase("\\fsm_encoding");
wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
module->wires_[wire->name] = wire;
@ -442,15 +442,15 @@ struct FsmExtractPass : public Pass {
assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") &&
cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) &&
cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
if (cell->type == "$pmux") {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S"));
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
if (bit1 != bit2)
@ -460,7 +460,7 @@ struct FsmExtractPass : public Pass {
std::vector<RTLIL::Wire*> wire_list;
for (auto &wire_it : module->wires_)
if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none")
if (design->selected(module, wire_it.second))
wire_list.push_back(wire_it.second);
for (auto wire : wire_list)

34
passes/fsm/fsm_map.cc
View file

@ -75,9 +75,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
eq_cell->setPort("\\A", eq_sig_a);
eq_cell->setPort("\\B", eq_sig_b);
eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
@ -103,8 +103,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
or_cell->setPort("\\A", or_sig);
or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@ -119,9 +119,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
and_cell->setPort("\\A", and_sig.extract(0, 1));
and_cell->setPort("\\B", and_sig.extract(1, 1));
and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@ -142,8 +142,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
or_cell->setPort("\\A", cases_vector);
or_cell->setPort("\\Y", output);
or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@ -213,9 +213,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
eq_cell->setPort("\\A", sig_a);
eq_cell->setPort("\\B", sig_b);
eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@ -286,10 +286,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
mux_cell->setPort("\\A", sig_a);
mux_cell->setPort("\\B", sig_b);
mux_cell->setPort("\\S", sig_s);
mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
}

2
passes/fsm/fsm_recode.cc
View file

@ -53,7 +53,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding)
{
std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());