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kernel: use more ID::*

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This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
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10
passes/equiv/equiv_struct.cc
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@ -127,8 +127,8 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
@ -140,9 +140,9 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
module->connect(sig_y, sig_a);