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kernel: use more ID::*

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This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
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8
passes/cmds/chformal.cc
View file

@ -206,7 +206,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
while (true)
{
SigSpec A = sigmap(cell->getPort("\\A"));
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort("\\EN"));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
@ -223,7 +223,7 @@ struct ChformalPass : public Pass {
if (A_map.second != EN_map.second)
break;
cell->setPort("\\A", A_map.first);
cell->setPort(ID::A, A_map.first);
cell->setPort("\\EN", EN_map.first);
}
}
@ -233,7 +233,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort("\\A");
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort("\\EN");
Wire *new_a = module->addWire(NEW_ID);
@ -243,7 +243,7 @@ struct ChformalPass : public Pass {
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort("\\A", new_a);
cell->setPort(ID::A, new_a);
cell->setPort("\\EN", new_en);
}
}

6
passes/cmds/design.cc
View file

@ -207,7 +207,7 @@ struct DesignPass : public Pass {
if (import_mode) {
for (auto module : copy_src_modules)
{
if (module->get_bool_attribute("\\top")) {
if (module->get_bool_attribute(ID::top)) {
copy_src_modules.clear();
copy_src_modules.push_back(module);
break;
@ -244,7 +244,7 @@ struct DesignPass : public Pass {
RTLIL::Module *t = mod->clone();
t->name = prefix;
t->design = copy_to_design;
t->attributes.erase("\\top");
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
@ -276,7 +276,7 @@ struct DesignPass : public Pass {
RTLIL::Module *t = fmod->clone();
t->name = trg_name;
t->design = copy_to_design;
t->attributes.erase("\\top");
t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);

4
passes/cmds/show.cc
View file

@ -482,8 +482,8 @@ struct ShowWorker
}
std::string proc_src = RTLIL::unescape_id(proc->name);
if (proc->attributes.count("\\src") > 0)
proc_src = proc->attributes.at("\\src").decode_string();
if (proc->attributes.count(ID::src) > 0)
proc_src = proc->attributes.at(ID::src).decode_string();
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str());
}

14
passes/cmds/splice.cc
View file

@ -79,9 +79,9 @@ struct SpliceWorker
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
cell->setPort("\\A", sig_a);
cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort("\\Y");
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
}
sliced_signals_cache[sig] = new_sig;
@ -135,10 +135,10 @@ struct SpliceWorker
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
cell->setPort("\\A", new_sig);
cell->setPort("\\B", sig2);
cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort("\\Y");
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
}
spliced_signals_cache[sig] = new_sig;

4
passes/cmds/splitnets.cc
View file

@ -60,8 +60,8 @@ struct SplitnetsWorker
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
if (wire->attributes.count("\\src"))
new_wire->attributes["\\src"] = wire->attributes.at("\\src");
if (wire->attributes.count(ID::src))
new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
if (wire->attributes.count("\\keep"))
new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");

10
passes/cmds/stat.cc
View file

@ -116,13 +116,13 @@ struct statdata_t
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) {
int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
}
@ -357,7 +357,7 @@ struct StatPass : public Pass {
for (auto mod : design->selected_modules())
{
if (!top_mod && design->full_selection())
if (mod->get_bool_attribute("\\top"))
if (mod->get_bool_attribute(ID::top))
top_mod = mod;
statdata_t data(design, mod, width_mode, cell_area, techname);