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kernel: use more ID::*

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This commit is contained in:
Eddie Hung 2020-03-12 12:57:01 -07:00
parent 164dd0f6b2
commit fdafb74eb7
69 changed files with 843 additions and 841 deletions
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104
frontends/liberty/liberty.cc
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@ -56,36 +56,36 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", A);
cell->setPort("\\Y", module->addWire(NEW_ID));
return cell->getPort("\\Y");
cell->setPort(ID::A, A);
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
cell->setPort("\\A", A);
cell->setPort("\\B", B);
cell->setPort("\\Y", module->addWire(NEW_ID));
return cell->getPort("\\Y");
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
cell->setPort("\\A", A);
cell->setPort("\\B", B);
cell->setPort("\\Y", module->addWire(NEW_ID));
return cell->getPort("\\Y");
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
cell->setPort("\\A", A);
cell->setPort("\\B", B);
cell->setPort("\\Y", module->addWire(NEW_ID));
return cell->getPort("\\Y");
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
@ -241,18 +241,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
clk_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clk_sig) {
clk_sig = it.second->getPort(ID::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
clear_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
preset_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
@ -260,8 +260,8 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", iq_sig);
cell->setPort("\\Y", iqn_sig);
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, "");
cell->setPort("\\D", data_sig);
@ -284,7 +284,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort("\\S", preset_sig);
cell->setPort(ID::S, preset_sig);
cell->setPort("\\R", clear_sig);
}
@ -324,18 +324,18 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
enable_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == enable_sig) {
enable_sig = it.second->getPort(ID::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
clear_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
preset_sig = it.second->getPort("\\A");
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
@ -343,8 +343,8 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", iq_sig);
cell->setPort("\\Y", iqn_sig);
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
if (clear_sig.size() == 1)
{
@ -354,24 +354,24 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
inv->setPort("\\A", clear_sig);
inv->setPort("\\Y", module->addWire(NEW_ID));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
if (clear_polarity == true)
clear_negative = inv->getPort("\\Y");
clear_negative = inv->getPort(ID::Y);
if (clear_polarity != enable_polarity)
clear_enable = inv->getPort("\\Y");
clear_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
data_gate->setPort("\\A", data_sig);
data_gate->setPort("\\B", clear_negative);
data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->setPort("\\A", enable_sig);
enable_gate->setPort("\\B", clear_enable);
enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
if (preset_sig.size() == 1)
@ -382,24 +382,24 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
inv->setPort("\\A", preset_sig);
inv->setPort("\\Y", module->addWire(NEW_ID));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
if (preset_polarity == false)
preset_positive = inv->getPort("\\Y");
preset_positive = inv->getPort(ID::Y);
if (preset_polarity != enable_polarity)
preset_enable = inv->getPort("\\Y");
preset_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
data_gate->setPort("\\A", data_sig);
data_gate->setPort("\\B", preset_positive);
data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->setPort("\\A", enable_sig);
enable_gate->setPort("\\B", preset_enable);
enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));