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kernel: use more ID::*
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parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -216,7 +216,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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for (auto cell : module->cells())
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if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
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module->connect(cell->getPort("\\Y"), cell->getPort("\\A"));
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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remove_cells.push_back(cell);
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}
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@ -488,8 +488,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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sopcell->parameters["\\DEPTH"] = 0;
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sopcell->parameters["\\TABLE"] = RTLIL::Const();
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sopcell->setPort("\\A", input_sig);
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sopcell->setPort("\\Y", output_sig);
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sopcell->setPort(ID::A, input_sig);
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sopcell->setPort(ID::Y, output_sig);
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sopmode = -1;
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lastcell = sopcell;
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}
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@ -498,8 +498,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
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cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->setPort("\\A", input_sig);
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cell->setPort("\\Y", output_sig);
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cell->setPort(ID::A, input_sig);
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cell->setPort(ID::Y, output_sig);
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lutptr = &cell->parameters.at("\\LUT");
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lut_default_state = RTLIL::State::Sx;
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lastcell = cell;
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@ -545,10 +545,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (sopmode == -1) {
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sopmode = (*output == '1');
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if (!sopmode) {
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SigSpec outnet = sopcell->getPort("\\Y");
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SigSpec outnet = sopcell->getPort(ID::Y);
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SigSpec tempnet = module->addWire(NEW_ID);
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module->addNotGate(NEW_ID, tempnet, outnet);
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sopcell->setPort("\\Y", tempnet);
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sopcell->setPort(ID::Y, tempnet);
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}
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} else
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log_assert(sopmode == (*output == '1'));
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