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https://github.com/YosysHQ/yosys
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kernel: use more ID::*
This commit is contained in:
Eddie Hung
parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -47,10 +47,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (gen_attributes)
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for (auto &attr : that->attributes) {
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@ -61,10 +61,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
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cell->setPort("\\A", arg);
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cell->setPort(ID::A, arg);
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cell->parameters["\\Y_WIDTH"] = result_width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -80,10 +80,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (that != NULL)
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for (auto &attr : that->attributes) {
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@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
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cell->setPort("\\A", sig);
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cell->setPort(ID::A, sig);
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cell->parameters["\\Y_WIDTH"] = width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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sig = wire;
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}
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@ -108,10 +108,10 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -125,11 +125,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
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cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
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cell->setPort("\\A", left);
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cell->setPort("\\B", right);
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cell->setPort(ID::A, left);
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cell->setPort(ID::B, right);
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cell->parameters["\\Y_WIDTH"] = result_width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -142,10 +142,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -155,10 +155,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
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cell->setPort("\\A", right);
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cell->setPort("\\B", left);
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cell->setPort("\\S", cond);
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cell->setPort("\\Y", wire);
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cell->setPort(ID::A, right);
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cell->setPort(ID::B, left);
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cell->setPort(ID::S, cond);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -199,7 +199,7 @@ struct AST_INTERNAL::ProcessGenerator
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{
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// generate process and simple root case
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proc = new RTLIL::Process;
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proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -221,7 +221,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto child : always->children)
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{
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if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
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child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
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child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
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found_global_syncs = true;
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}
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if (child->type == AST_EDGE) {
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@ -245,7 +245,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto child : always->children)
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if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
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if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
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child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
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child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
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continue;
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found_clocked_sync = true;
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if (found_global_syncs || found_anyedge_syncs)
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@ -335,7 +335,7 @@ struct AST_INTERNAL::ProcessGenerator
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} while (current_module->wires_.count(wire_name) > 0);
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RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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chunk.wire = wire;
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chunk.offset = 0;
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@ -470,7 +470,7 @@ struct AST_INTERNAL::ProcessGenerator
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case AST_CASE:
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{
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RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
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sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
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sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
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sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
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current_case->switches.push_back(sw);
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@ -504,7 +504,7 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
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current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
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last_generated_case = current_case;
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addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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for (auto node : child->children) {
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@ -525,7 +525,7 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.restore();
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}
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if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
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if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
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#if 0
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// this is a valid transformation, but as optimization it is premature.
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// better: add a default case that assigns 'x' to everything, and let later
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@ -873,12 +873,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// This is used by the hierarchy pass to know when it can replace interface connection with the individual
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// signals.
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RTLIL::Wire *wire = current_module->addWire(str, 1);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->start_offset = 0;
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wire->port_id = port_id;
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wire->port_input = true;
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wire->port_output = true;
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wire->set_bool_attribute("\\is_interface");
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wire->set_bool_attribute(ID::is_interface);
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if (children.size() > 0) {
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for(size_t i=0; i<children.size();i++) {
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if(children[i]->type == AST_INTERFACEPORTTYPE) {
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@ -910,7 +910,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
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current_module->connect(wire, val);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
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for (auto &attr : attributes) {
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@ -932,7 +932,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
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RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->start_offset = range_right;
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wire->port_id = port_id;
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wire->port_input = is_input;
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@ -945,8 +945,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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wire->attributes[attr.first] = attr.second->asAttrConst();
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}
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if (is_wand) wire->set_bool_attribute("\\wand");
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if (is_wor) wire->set_bool_attribute("\\wor");
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if (is_wand) wire->set_bool_attribute(ID::wand);
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if (is_wor) wire->set_bool_attribute(ID::wor);
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}
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break;
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@ -963,7 +963,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
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RTLIL::Memory *memory = new RTLIL::Memory;
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memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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memory->name = str;
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memory->width = children[0]->range_left - children[0]->range_right + 1;
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if (children[1]->range_right < children[1]->range_left) {
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@ -1018,7 +1018,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
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RTLIL::Wire *wire = current_module->addWire(str);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->name = str;
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if (flag_autowire)
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log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
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@ -1033,7 +1033,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
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RTLIL::Wire *current_wire = current_module->wire(str);
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if (current_wire->get_bool_attribute("\\is_interface"))
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if (current_wire->get_bool_attribute(ID::is_interface))
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is_interface = true;
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// Ignore
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}
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@ -1058,7 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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dummy_wire = current_module->wires_[dummy_wire_name];
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else {
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dummy_wire = current_module->addWire(dummy_wire_name);
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dummy_wire->set_bool_attribute("\\is_interface");
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dummy_wire->set_bool_attribute(ID::is_interface);
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}
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RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
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return tmp;
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@ -1375,10 +1375,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
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cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
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wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
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int mem_width, mem_size, addr_bits;
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is_signed = id2ast->is_signed;
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@ -1413,7 +1413,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
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cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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int mem_width, mem_size, addr_bits;
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id2ast->meminfo(mem_width, mem_size, addr_bits);
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@ -1480,7 +1480,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
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cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -1488,7 +1488,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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cell->setPort("\\A", check);
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cell->setPort(ID::A, check);
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cell->setPort("\\EN", en);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1525,7 +1525,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(str, "");
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
|
||||
cell->set_bool_attribute("\\module_not_derived");
|
||||
|
||||
|
|
@ -1668,7 +1668,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
|
||||
Cell *cell = current_module->addCell(myid, str.substr(1));
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->parameters["\\WIDTH"] = width;
|
||||
|
||||
if (attributes.count("\\reg")) {
|
||||
|
|
@ -1679,8 +1679,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
Wire *wire = current_module->addWire(myid + "_wire", width);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->setPort("\\Y", wire);
|
||||
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->setPort(ID::Y, wire);
|
||||
|
||||
is_signed = sign_hint;
|
||||
return SigSpec(wire);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue