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kernel: use more ID::*
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parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -952,7 +952,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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current_module = new AstModule;
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current_module->ast = NULL;
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current_module->name = ast->str;
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current_module->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
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current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
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ast->location.first_column, ast->location.last_line, ast->location.last_column);
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current_module->set_bool_attribute("\\cells_not_processed");
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@ -1124,7 +1124,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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}
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if (ast->type == AST_INTERFACE)
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current_module->set_bool_attribute("\\is_interface");
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current_module->set_bool_attribute(ID::is_interface);
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current_module->ast = ast_before_simplify;
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current_module->nolatches = flag_nolatches;
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current_module->nomeminit = flag_nomeminit;
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@ -1389,8 +1389,8 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
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// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
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// new module.
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if (this->get_bool_attribute("\\initial_top")) {
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this->attributes.erase("\\initial_top");
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if (this->get_bool_attribute(ID::initial_top)) {
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this->attributes.erase(ID::initial_top);
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is_top = true;
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}
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@ -1400,7 +1400,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
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design->add(newmod);
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RTLIL::Module* mod = design->module(original_name);
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if (is_top)
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mod->set_bool_attribute("\\top");
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mod->set_bool_attribute(ID::top);
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// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
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mod->set_bool_attribute("\\interfaces_replaced_in_module");
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@ -1473,7 +1473,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
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// We copy the cell of the interface to the sub-module such that it
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// can further be found if it is propagated down to sub-sub-modules etc.
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RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name);
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new_subcell->set_bool_attribute("\\is_interface");
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new_subcell->set_bool_attribute(ID::is_interface);
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}
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else {
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log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
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