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https://github.com/YosysHQ/yosys
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kernel: use more ID::*
This commit is contained in:
Eddie Hung
parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -367,15 +367,15 @@ struct Smt2Worker
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void export_gate(RTLIL::Cell *cell, std::string expr)
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{
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RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
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RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
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std::string processed_expr;
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for (char ch : expr) {
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if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A"));
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else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B"));
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if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
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else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
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else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C"));
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else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D"));
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else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S"));
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else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
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else processed_expr += ch;
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}
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@ -391,23 +391,23 @@ struct Smt2Worker
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void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
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{
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RTLIL::SigSpec sig_a, sig_b;
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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int width = GetSize(sig_y);
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if (type == 's' || type == 'd' || type == 'b') {
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width = max(width, GetSize(cell->getPort("\\A")));
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if (cell->hasPort("\\B"))
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width = max(width, GetSize(cell->getPort("\\B")));
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width = max(width, GetSize(cell->getPort(ID::A)));
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if (cell->hasPort(ID::B))
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width = max(width, GetSize(cell->getPort(ID::B)));
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}
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if (cell->hasPort("\\A")) {
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sig_a = cell->getPort("\\A");
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if (cell->hasPort(ID::A)) {
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sig_a = cell->getPort(ID::A);
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sig_a.extend_u0(width, is_signed);
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}
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if (cell->hasPort("\\B")) {
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sig_b = cell->getPort("\\B");
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if (cell->hasPort(ID::B)) {
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sig_b = cell->getPort(ID::B);
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sig_b.extend_u0(width, is_signed && !(type == 's'));
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}
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@ -416,7 +416,7 @@ struct Smt2Worker
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for (char ch : expr) {
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if (ch == 'A') processed_expr += get_bv(sig_a);
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else if (ch == 'B') processed_expr += get_bv(sig_b);
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else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B"));
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else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B));
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else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
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else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
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else processed_expr += ch;
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@ -443,7 +443,7 @@ struct Smt2Worker
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void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
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{
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
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std::string processed_expr;
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for (char ch : expr)
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@ -482,7 +482,7 @@ struct Smt2Worker
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if (cell->type == "$initstate")
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{
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SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
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SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
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get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit)));
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register_bool(bit, idcounter++);
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@ -532,22 +532,22 @@ struct Smt2Worker
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if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
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{
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registers.insert(cell);
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string infostr = cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell);
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string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell);
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if (cell->attributes.count("\\reg"))
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infostr += " " + cell->attributes.at("\\reg").decode_string();
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decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str()));
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if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){
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decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str()));
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if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\maximize")){
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decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
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log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
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log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
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}
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else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){
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else if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\minimize")){
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decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
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log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
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log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
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}
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y)));
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if (cell->type == "$anyseq")
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ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
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register_bv(cell->getPort("\\Y"), idcounter++);
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register_bv(cell->getPort(ID::Y), idcounter++);
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recursive_cells.erase(cell);
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return;
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}
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@ -566,7 +566,7 @@ struct Smt2Worker
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if (cell->getParam("\\B_SIGNED").as_bool()) {
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return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
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"(bvlshr A B) (bvlshr A (bvneg B)))",
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GetSize(cell->getPort("\\B")), 0), 's');
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GetSize(cell->getPort(ID::B)), 0), 's');
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} else {
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return export_bvop(cell, "(bvlshr A B)", 's');
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}
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@ -593,9 +593,9 @@ struct Smt2Worker
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if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd');
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if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
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2*GetSize(cell->getPort("\\A").chunks()) < GetSize(cell->getPort("\\A"))) {
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2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
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bool is_and = cell->type == "$reduce_and";
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string bits(GetSize(cell->getPort("\\A")), is_and ? '1' : '0');
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string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
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return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b');
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}
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@ -611,11 +611,11 @@ struct Smt2Worker
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if (cell->type.in("$mux", "$pmux"))
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{
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int width = GetSize(cell->getPort("\\Y"));
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std::string processed_expr = get_bv(cell->getPort("\\A"));
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int width = GetSize(cell->getPort(ID::Y));
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std::string processed_expr = get_bv(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_s = cell->getPort("\\S");
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::SigSpec sig_s = cell->getPort(ID::S);
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get_bv(sig_b);
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get_bv(sig_s);
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@ -626,7 +626,7 @@ struct Smt2Worker
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if (verbose)
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log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
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RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y"));
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RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig)));
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register_bv(sig, idcounter++);
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@ -895,9 +895,9 @@ struct Smt2Worker
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cell->type == "$assume" ? 'u' :
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cell->type == "$cover" ? 'c' : 0;
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string name_a = get_bool(cell->getPort("\\A"));
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string name_a = get_bool(cell->getPort(ID::A));
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string name_en = get_bool(cell->getPort("\\EN"));
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string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell);
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string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell);
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decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
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if (cell->type == "$cover")
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@ -983,11 +983,11 @@ struct Smt2Worker
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if (cell->type.in("$anyconst", "$allconst"))
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{
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std::string expr_d = get_bv(cell->getPort("\\Y"));
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std::string expr_q = get_bv(cell->getPort("\\Y"), "next_state");
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trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Y"))));
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std::string expr_d = get_bv(cell->getPort(ID::Y));
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std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
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trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y))));
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if (cell->type == "$anyconst")
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ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Y")).c_str(), get_bv(cell->getPort("\\Y"), "other_state").c_str()));
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ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str()));
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}
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if (cell->type == "$mem")
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