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Make SigSpec::updhash() use chunk iterator
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parent
37e4c2e8f8
commit
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1 changed files with 5 additions and 9 deletions
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@ -4736,10 +4736,9 @@ void RTLIL::SigSpec::updhash() const
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return;
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return;
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cover("kernel.rtlil.sigspec.hash");
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cover("kernel.rtlil.sigspec.hash");
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that->pack();
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Hasher h;
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Hasher h;
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for (auto &c : that->chunks_)
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for (auto &c : that->chunks())
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if (c.wire == NULL) {
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if (c.wire == NULL) {
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for (auto &v : c.data)
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for (auto &v : c.data)
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h.eat(v);
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h.eat(v);
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@ -5193,13 +5192,8 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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cover("kernel.rtlil.sigspec.append");
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cover("kernel.rtlil.sigspec.append");
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if (packed() != signal.packed()) {
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pack();
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signal.pack();
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}
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if (packed())
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if (packed())
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for (auto &other_c : signal.chunks_)
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for (auto &other_c : signal.chunks())
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{
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{
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auto &my_last_c = chunks_.back();
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auto &my_last_c = chunks_.back();
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if (my_last_c.wire == NULL && other_c.wire == NULL) {
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if (my_last_c.wire == NULL && other_c.wire == NULL) {
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@ -5213,8 +5207,10 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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} else
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} else
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chunks_.push_back(other_c);
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chunks_.push_back(other_c);
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}
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}
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else
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else {
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signal.unpack();
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bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
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bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
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}
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width_ += signal.width_;
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width_ += signal.width_;
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check();
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check();
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