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Add v2 memory cells.

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This commit is contained in:
Marcelina Kościelnicka 2021-05-27 20:54:29 +02:00
parent b96eb888cc
commit fd79217763
22 changed files with 631 additions and 206 deletions
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2
tests/svtypes/logic_rom.ys
View file

@ -1,3 +1,3 @@
read_verilog -sv logic_rom.sv
prep -top top
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i
select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=8 %i

2
tests/svtypes/typedef_memory.ys
View file

@ -1,3 +1,3 @@
read_verilog -sv typedef_memory.sv
prep -top top
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i

2
tests/svtypes/typedef_memory_2.ys
View file

@ -1,4 +1,4 @@
read_verilog -sv typedef_memory_2.sv
prep -top top
dump
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i