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Add v2 memory cells.
This commit is contained in:
Marcelina Kościelnicka
parent
b96eb888cc
commit
fd79217763
22 changed files with 631 additions and 206 deletions
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@ -2182,6 +2182,34 @@ end
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endmodule
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module \$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);
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parameter MEMID = "";
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parameter ABITS = 8;
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parameter WIDTH = 8;
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parameter CLK_ENABLE = 0;
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parameter CLK_POLARITY = 0;
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parameter TRANSPARENCY_MASK = 0;
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parameter COLLISION_X_MASK = 0;
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parameter ARST_VALUE = 0;
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parameter SRST_VALUE = 0;
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parameter INIT_VALUE = 0;
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parameter CE_OVER_SRST = 0;
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input CLK, EN, ARST, SRST;
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input [ABITS-1:0] ADDR;
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output [WIDTH-1:0] DATA;
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initial begin
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if (MEMID != "") begin
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$display("ERROR: Found non-simulatable instance of $memrd_v2!");
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$finish;
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end
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end
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endmodule
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// --------------------------------------------------------
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module \$memwr (CLK, EN, ADDR, DATA);
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@ -2208,6 +2236,31 @@ end
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endmodule
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module \$memwr_v2 (CLK, EN, ADDR, DATA);
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parameter MEMID = "";
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parameter ABITS = 8;
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parameter WIDTH = 8;
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parameter CLK_ENABLE = 0;
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parameter CLK_POLARITY = 0;
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parameter PORTID = 0;
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parameter PRIORITY_MASK = 0;
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input CLK;
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input [WIDTH-1:0] EN;
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input [ABITS-1:0] ADDR;
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input [WIDTH-1:0] DATA;
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initial begin
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if (MEMID != "") begin
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$display("ERROR: Found non-simulatable instance of $memwr_v2!");
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$finish;
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end
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end
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endmodule
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// --------------------------------------------------------
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module \$meminit (ADDR, DATA);
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@ -2344,6 +2397,122 @@ end
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endmodule
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module \$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
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parameter MEMID = "";
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parameter signed SIZE = 4;
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parameter signed OFFSET = 0;
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parameter signed ABITS = 2;
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parameter signed WIDTH = 8;
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parameter signed INIT = 1'bx;
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parameter signed RD_PORTS = 1;
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parameter RD_CLK_ENABLE = 1'b1;
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parameter RD_CLK_POLARITY = 1'b1;
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parameter RD_TRANSPARENCY_MASK = 1'b0;
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parameter RD_COLLISION_X_MASK = 1'b0;
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parameter RD_WIDE_CONTINUATION = 1'b0;
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parameter RD_CE_OVER_SRST = 1'b0;
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parameter RD_ARST_VALUE = 1'b0;
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parameter RD_SRST_VALUE = 1'b0;
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parameter RD_INIT_VALUE = 1'b0;
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parameter signed WR_PORTS = 1;
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parameter WR_CLK_ENABLE = 1'b1;
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parameter WR_CLK_POLARITY = 1'b1;
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parameter WR_PRIORITY_MASK = 1'b0;
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parameter WR_WIDE_CONTINUATION = 1'b0;
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input [RD_PORTS-1:0] RD_CLK;
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input [RD_PORTS-1:0] RD_EN;
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input [RD_PORTS-1:0] RD_ARST;
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input [RD_PORTS-1:0] RD_SRST;
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input [RD_PORTS*ABITS-1:0] RD_ADDR;
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output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
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input [WR_PORTS-1:0] WR_CLK;
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input [WR_PORTS*WIDTH-1:0] WR_EN;
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input [WR_PORTS*ABITS-1:0] WR_ADDR;
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input [WR_PORTS*WIDTH-1:0] WR_DATA;
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reg [WIDTH-1:0] memory [SIZE-1:0];
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integer i, j, k;
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reg [WR_PORTS-1:0] LAST_WR_CLK;
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reg [RD_PORTS-1:0] LAST_RD_CLK;
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function port_active;
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input clk_enable;
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input clk_polarity;
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input last_clk;
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input this_clk;
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begin
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casez ({clk_enable, clk_polarity, last_clk, this_clk})
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4'b0???: port_active = 1;
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4'b1101: port_active = 1;
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4'b1010: port_active = 1;
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default: port_active = 0;
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endcase
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end
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endfunction
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initial begin
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for (i = 0; i < SIZE; i = i+1)
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memory[i] = INIT >>> (i*WIDTH);
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RD_DATA = RD_INIT_VALUE;
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end
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always @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
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`ifdef SIMLIB_MEMDELAY
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#`SIMLIB_MEMDELAY;
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`endif
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
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// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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for (j = 0; j < WR_PORTS; j = j+1) begin
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if (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])
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for (k = 0; k < WIDTH; k = k+1)
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if (WR_EN[j*WIDTH+k])
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RD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];
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if (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])
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for (k = 0; k < WIDTH; k = k+1)
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if (WR_EN[j*WIDTH+k])
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RD_DATA[i*WIDTH+k] <= 1'bx;
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end
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end
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end
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for (i = 0; i < WR_PORTS; i = i+1) begin
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if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
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for (j = 0; j < WIDTH; j = j+1)
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if (WR_EN[i*WIDTH+j]) begin
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// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
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memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
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end
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end
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if (!RD_CLK_ENABLE[i]) begin
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// $display("Combinatorial read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end
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end
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))
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RD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];
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if (RD_ARST[i])
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RD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];
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end
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LAST_RD_CLK <= RD_CLK;
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LAST_WR_CLK <= WR_CLK;
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end
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endmodule
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`endif
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// --------------------------------------------------------
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