mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-25 13:47:02 +00:00
Code Activity

Add v2 memory cells.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-05-27 20:54:29 +02:00
parent b96eb888cc
commit fd79217763
22 changed files with 631 additions and 206 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/opt/opt_reduce.cc
View file

@ -254,9 +254,9 @@ struct OptReduceWorker
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mem))
if (cell->type.in(ID($mem), ID($mem_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
if (cell->type == ID($memwr))
if (cell->type.in(ID($memwr), ID($memwr_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
}
for (auto &cell_it : module->cells_) {