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Add v2 memory cells.

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This commit is contained in:
Marcelina Kościelnicka 2021-05-27 20:54:29 +02:00
parent b96eb888cc
commit fd79217763
22 changed files with 631 additions and 206 deletions
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70
kernel/rtlil.cc
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@ -1392,6 +1392,26 @@ namespace {
return;
}
if (cell->type == ID($memrd_v2)) {
param(ID::MEMID);
param_bool(ID::CLK_ENABLE);
param_bool(ID::CLK_POLARITY);
param(ID::TRANSPARENCY_MASK);
param(ID::COLLISION_X_MASK);
param_bool(ID::CE_OVER_SRST);
param_bits(ID::ARST_VALUE, param(ID::WIDTH));
param_bits(ID::SRST_VALUE, param(ID::WIDTH));
param_bits(ID::INIT_VALUE, param(ID::WIDTH));
port(ID::CLK, 1);
port(ID::EN, 1);
port(ID::ARST, 1);
port(ID::SRST, 1);
port(ID::ADDR, param(ID::ABITS));
port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($memwr)) {
param(ID::MEMID);
param_bool(ID::CLK_ENABLE);
@ -1405,6 +1425,20 @@ namespace {
return;
}
if (cell->type == ID($memwr_v2)) {
param(ID::MEMID);
param_bool(ID::CLK_ENABLE);
param_bool(ID::CLK_POLARITY);
param(ID::PORTID);
param(ID::PRIORITY_MASK);
port(ID::CLK, 1);
port(ID::EN, param(ID::WIDTH));
port(ID::ADDR, param(ID::ABITS));
port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($meminit)) {
param(ID::MEMID);
param(ID::PRIORITY);
@ -1446,6 +1480,38 @@ namespace {
return;
}
if (cell->type == ID($mem_v2)) {
param(ID::MEMID);
param(ID::SIZE);
param(ID::OFFSET);
param(ID::INIT);
param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_TRANSPARENCY_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_PRIORITY_MASK, max(1, param(ID::WR_PORTS) * param(ID::WR_PORTS)));
port(ID::RD_CLK, param(ID::RD_PORTS));
port(ID::RD_EN, param(ID::RD_PORTS));
port(ID::RD_ARST, param(ID::RD_PORTS));
port(ID::RD_SRST, param(ID::RD_PORTS));
port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
port(ID::WR_CLK, param(ID::WR_PORTS));
port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($tribuf)) {
port(ID::A, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
@ -3187,12 +3253,12 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
bool RTLIL::Cell::has_memid() const
{
return type.in(ID($memwr), ID($memrd), ID($meminit), ID($meminit_v2));
return type.in(ID($memwr), ID($memwr_v2), ID($memrd), ID($memrd_v2), ID($meminit), ID($meminit_v2));
}
bool RTLIL::Cell::is_mem_cell() const
{
return type == ID($mem) || has_memid();
return type.in(ID($mem), ID($mem_v2)) || has_memid();
}
RTLIL::SigChunk::SigChunk()