mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-22 13:53:40 +00:00
Add v2 memory cells.
This commit is contained in:
Marcelina Kościelnicka
parent
b96eb888cc
commit
fd79217763
22 changed files with 631 additions and 206 deletions
359
kernel/mem.cc
359
kernel/mem.cc
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@ -123,42 +123,31 @@ void Mem::emit() {
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if (!cell) {
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if (memid.empty())
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memid = NEW_ID;
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cell = module->addCell(memid, ID($mem));
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cell = module->addCell(memid, ID($mem_v2));
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}
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cell->type = ID($mem_v2);
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cell->attributes = attributes;
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cell->parameters[ID::MEMID] = Const(memid.str());
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cell->parameters[ID::WIDTH] = Const(width);
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cell->parameters[ID::OFFSET] = Const(start_offset);
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cell->parameters[ID::SIZE] = Const(size);
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Const rd_wide_continuation, rd_clk_enable, rd_clk_polarity, rd_transparent;
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Const wr_wide_continuation, wr_clk_enable, wr_clk_polarity;
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Const rd_wide_continuation, rd_clk_enable, rd_clk_polarity, rd_transparency_mask, rd_collision_x_mask;
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Const wr_wide_continuation, wr_clk_enable, wr_clk_polarity, wr_priority_mask;
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Const rd_ce_over_srst, rd_arst_value, rd_srst_value, rd_init_value;
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SigSpec rd_clk, rd_en, rd_addr, rd_data;
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SigSpec wr_clk, wr_en, wr_addr, wr_data;
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SigSpec rd_arst, rd_srst;
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int abits = 0;
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for (auto &port : rd_ports)
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abits = std::max(abits, GetSize(port.addr));
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for (auto &port : wr_ports)
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abits = std::max(abits, GetSize(port.addr));
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cell->parameters[ID::ABITS] = Const(abits);
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std::vector<int> wr_port_xlat;
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for (int i = 0; i < GetSize(wr_ports); i++)
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for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++)
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wr_port_xlat.push_back(i);
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for (auto &port : rd_ports) {
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// TODO: remove
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log_assert(port.arst == State::S0);
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log_assert(port.srst == State::S0);
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log_assert(port.init_value == Const(State::Sx, width << port.wide_log2));
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bool transparent = false;
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bool non_transparent = false;
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if (port.clk_enable) {
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for (int i = 0; i < GetSize(wr_ports); i++) {
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auto &oport = wr_ports[i];
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if (oport.clk_enable && oport.clk == port.clk && oport.clk_polarity == port.clk_polarity) {
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if (port.transparency_mask[i])
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transparent = true;
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else if (!port.collision_x_mask[i])
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non_transparent = true;
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}
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}
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log_assert(!transparent || !non_transparent);
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}
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if (port.cell) {
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module->remove(port.cell);
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port.cell = nullptr;
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@ -168,28 +157,55 @@ void Mem::emit() {
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rd_wide_continuation.bits.push_back(State(sub != 0));
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rd_clk_enable.bits.push_back(State(port.clk_enable));
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rd_clk_polarity.bits.push_back(State(port.clk_polarity));
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rd_transparent.bits.push_back(State(transparent));
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rd_ce_over_srst.bits.push_back(State(port.ce_over_srst));
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rd_clk.append(port.clk);
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rd_arst.append(port.arst);
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rd_srst.append(port.srst);
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rd_en.append(port.en);
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SigSpec addr = port.sub_addr(sub);
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addr.extend_u0(abits, false);
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rd_addr.append(addr);
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log_assert(GetSize(addr) == abits);
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for (auto idx : wr_port_xlat) {
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rd_transparency_mask.bits.push_back(State(bool(port.transparency_mask[idx])));
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rd_collision_x_mask.bits.push_back(State(bool(port.collision_x_mask[idx])));
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}
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}
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rd_data.append(port.data);
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for (auto &bit : port.arst_value)
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rd_arst_value.bits.push_back(bit);
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for (auto &bit : port.srst_value)
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rd_srst_value.bits.push_back(bit);
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for (auto &bit : port.init_value)
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rd_init_value.bits.push_back(bit);
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}
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if (rd_ports.empty()) {
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rd_wide_continuation = State::S0;
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rd_clk_enable = State::S0;
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rd_clk_polarity = State::S0;
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rd_transparent = State::S0;
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rd_ce_over_srst = State::S0;
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rd_arst_value = State::S0;
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rd_srst_value = State::S0;
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rd_init_value = State::S0;
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}
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if (rd_ports.empty() || wr_ports.empty()) {
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rd_transparency_mask = State::S0;
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rd_collision_x_mask = State::S0;
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}
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cell->parameters[ID::RD_PORTS] = Const(GetSize(rd_clk));
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cell->parameters[ID::RD_CLK_ENABLE] = rd_clk_enable;
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cell->parameters[ID::RD_CLK_POLARITY] = rd_clk_polarity;
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cell->parameters[ID::RD_TRANSPARENT] = rd_transparent;
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cell->parameters[ID::RD_TRANSPARENCY_MASK] = rd_transparency_mask;
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cell->parameters[ID::RD_COLLISION_X_MASK] = rd_collision_x_mask;
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cell->parameters[ID::RD_WIDE_CONTINUATION] = rd_wide_continuation;
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cell->parameters[ID::RD_CE_OVER_SRST] = rd_ce_over_srst;
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cell->parameters[ID::RD_ARST_VALUE] = rd_arst_value;
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cell->parameters[ID::RD_SRST_VALUE] = rd_srst_value;
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cell->parameters[ID::RD_INIT_VALUE] = rd_init_value;
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cell->setPort(ID::RD_CLK, rd_clk);
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cell->setPort(ID::RD_EN, rd_en);
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cell->setPort(ID::RD_ARST, rd_arst);
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cell->setPort(ID::RD_SRST, rd_srst);
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cell->setPort(ID::RD_ADDR, rd_addr);
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cell->setPort(ID::RD_DATA, rd_data);
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for (auto &port : wr_ports) {
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@ -203,6 +219,8 @@ void Mem::emit() {
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wr_clk_enable.bits.push_back(State(port.clk_enable));
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wr_clk_polarity.bits.push_back(State(port.clk_polarity));
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wr_clk.append(port.clk);
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for (auto idx : wr_port_xlat)
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wr_priority_mask.bits.push_back(State(bool(port.priority_mask[idx])));
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SigSpec addr = port.sub_addr(sub);
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addr.extend_u0(abits, false);
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wr_addr.append(addr);
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@ -215,10 +233,13 @@ void Mem::emit() {
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wr_wide_continuation = State::S0;
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wr_clk_enable = State::S0;
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wr_clk_polarity = State::S0;
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wr_priority_mask = State::S0;
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}
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cell->parameters[ID::WR_PORTS] = Const(GetSize(wr_clk));
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cell->parameters[ID::WR_CLK_ENABLE] = wr_clk_enable;
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cell->parameters[ID::WR_CLK_POLARITY] = wr_clk_polarity;
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cell->parameters[ID::WR_PRIORITY_MASK] = wr_priority_mask;
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cell->parameters[ID::WR_WIDE_CONTINUATION] = wr_wide_continuation;
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cell->setPort(ID::WR_CLK, wr_clk);
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cell->setPort(ID::WR_EN, wr_en);
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cell->setPort(ID::WR_ADDR, wr_addr);
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@ -247,49 +268,44 @@ void Mem::emit() {
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mem->size = size;
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mem->attributes = attributes;
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for (auto &port : rd_ports) {
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// TODO: remove
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log_assert(port.arst == State::S0);
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log_assert(port.srst == State::S0);
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log_assert(port.init_value == Const(State::Sx, width << port.wide_log2));
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bool transparent = false;
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bool non_transparent = false;
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if (port.clk_enable) {
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for (int i = 0; i < GetSize(wr_ports); i++) {
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auto &oport = wr_ports[i];
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if (oport.clk_enable && oport.clk == port.clk && oport.clk_polarity == port.clk_polarity) {
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if (port.transparency_mask[i])
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transparent = true;
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else if (!port.collision_x_mask[i])
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non_transparent = true;
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}
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}
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log_assert(!transparent || !non_transparent);
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}
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memrd));
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port.cell = module->addCell(NEW_ID, ID($memrd_v2));
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port.cell->type = ID($memrd_v2);
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port.cell->attributes = port.attributes;
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::CLK_ENABLE] = port.clk_enable;
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port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
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port.cell->parameters[ID::TRANSPARENT] = transparent;
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port.cell->parameters[ID::CE_OVER_SRST] = port.ce_over_srst;
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port.cell->parameters[ID::ARST_VALUE] = port.arst_value;
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port.cell->parameters[ID::SRST_VALUE] = port.srst_value;
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port.cell->parameters[ID::INIT_VALUE] = port.init_value;
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port.cell->parameters[ID::TRANSPARENCY_MASK] = port.transparency_mask;
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port.cell->parameters[ID::COLLISION_X_MASK] = port.collision_x_mask;
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port.cell->parameters.erase(ID::TRANSPARENT);
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port.cell->setPort(ID::CLK, port.clk);
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port.cell->setPort(ID::EN, port.en);
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port.cell->setPort(ID::ARST, port.arst);
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port.cell->setPort(ID::SRST, port.srst);
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port.cell->setPort(ID::ADDR, port.addr);
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port.cell->setPort(ID::DATA, port.data);
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}
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int idx = 0;
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for (auto &port : wr_ports) {
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memwr));
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port.cell = module->addCell(NEW_ID, ID($memwr_v2));
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port.cell->type = ID($memwr_v2);
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port.cell->attributes = port.attributes;
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if (port.cell->parameters.count(ID::PRIORITY))
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port.cell->parameters.erase(ID::PRIORITY);
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::CLK_ENABLE] = port.clk_enable;
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port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
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port.cell->parameters[ID::PRIORITY] = idx++;
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port.cell->parameters[ID::PORTID] = idx++;
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port.cell->parameters[ID::PRIORITY_MASK] = port.priority_mask;
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port.cell->setPort(ID::CLK, port.clk);
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port.cell->setPort(ID::EN, port.en);
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port.cell->setPort(ID::ADDR, port.addr);
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@ -497,9 +513,9 @@ namespace {
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dict<IdString, pool<Cell *>> inits;
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MemIndex (Module *module) {
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for (auto cell: module->cells()) {
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if (cell->type == ID($memwr))
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if (cell->type.in(ID($memwr), ID($memwr_v2)))
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wr_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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else if (cell->type == ID($memrd))
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else if (cell->type.in(ID($memrd), ID($memrd_v2)))
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rd_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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else if (cell->type.in(ID($meminit), ID($meminit_v2)))
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inits[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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@ -513,33 +529,45 @@ namespace {
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res.mem = mem;
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res.attributes = mem->attributes;
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std::vector<bool> rd_transparent;
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std::vector<int> wr_portid;
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if (index.rd_ports.count(mem->name)) {
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for (auto cell : index.rd_ports.at(mem->name)) {
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MemRd mrd;
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bool is_compat = cell->type == ID($memrd);
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mrd.cell = cell;
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mrd.attributes = cell->attributes;
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mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
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mrd.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
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bool transparent = cell->parameters.at(ID::TRANSPARENT).as_bool();
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mrd.clk = cell->getPort(ID::CLK);
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mrd.en = cell->getPort(ID::EN);
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mrd.addr = cell->getPort(ID::ADDR);
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mrd.data = cell->getPort(ID::DATA);
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mrd.wide_log2 = ceil_log2(GetSize(mrd.data) / mem->width);
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mrd.ce_over_srst = false;
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mrd.arst_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.srst_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.init_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.srst = State::S0;
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mrd.arst = State::S0;
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if (!mrd.clk_enable) {
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// Fix some patterns that we'll allow for backwards compatibility,
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// but don't want to see moving forwards: async transparent
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// ports (inherently meaningless) and async ports without
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// const 1 tied to EN bit (which may mean a latch in the future).
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transparent = false;
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if (mrd.en == State::Sx)
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mrd.en = State::S1;
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bool transparent = false;
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if (is_compat) {
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transparent = cell->parameters.at(ID::TRANSPARENT).as_bool();
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mrd.ce_over_srst = false;
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mrd.arst_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.srst_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.init_value = Const(State::Sx, mem->width << mrd.wide_log2);
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mrd.srst = State::S0;
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mrd.arst = State::S0;
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if (!mrd.clk_enable) {
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// Fix some patterns that we'll allow for backwards compatibility,
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// but don't want to see moving forwards: async transparent
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// ports (inherently meaningless) and async ports without
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// const 1 tied to EN bit (which may mean a latch in the future).
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transparent = false;
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if (mrd.en == State::Sx)
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mrd.en = State::S1;
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}
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} else {
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mrd.ce_over_srst = cell->parameters.at(ID::CE_OVER_SRST).as_bool();
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mrd.arst_value = cell->parameters.at(ID::ARST_VALUE);
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mrd.srst_value = cell->parameters.at(ID::SRST_VALUE);
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mrd.init_value = cell->parameters.at(ID::INIT_VALUE);
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mrd.arst = cell->getPort(ID::ARST);
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mrd.srst = cell->getPort(ID::SRST);
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}
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res.rd_ports.push_back(mrd);
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rd_transparent.push_back(transparent);
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@ -549,6 +577,7 @@ namespace {
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std::vector<std::pair<int, MemWr>> ports;
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for (auto cell : index.wr_ports.at(mem->name)) {
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MemWr mwr;
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bool is_compat = cell->type == ID($memwr);
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mwr.cell = cell;
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mwr.attributes = cell->attributes;
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mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
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@ -558,11 +587,36 @@ namespace {
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mwr.addr = cell->getPort(ID::ADDR);
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mwr.data = cell->getPort(ID::DATA);
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mwr.wide_log2 = ceil_log2(GetSize(mwr.data) / mem->width);
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ports.push_back(std::make_pair(cell->parameters.at(ID::PRIORITY).as_int(), mwr));
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ports.push_back(std::make_pair(cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int(), mwr));
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}
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std::sort(ports.begin(), ports.end(), [](const std::pair<int, MemWr> &a, const std::pair<int, MemWr> &b) { return a.first < b.first; });
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for (auto &it : ports)
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for (auto &it : ports) {
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res.wr_ports.push_back(it.second);
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wr_portid.push_back(it.first);
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}
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for (int i = 0; i < GetSize(res.wr_ports); i++) {
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auto &port = res.wr_ports[i];
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bool is_compat = port.cell->type == ID($memwr);
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if (is_compat) {
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port.priority_mask.resize(GetSize(res.wr_ports));
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for (int j = 0; j < i; j++) {
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auto &oport = res.wr_ports[j];
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if (port.clk_enable != oport.clk_enable)
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continue;
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if (port.clk_enable && port.clk != oport.clk)
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continue;
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if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
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continue;
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port.priority_mask[j] = true;
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}
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} else {
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Const orig_prio_mask = port.cell->parameters.at(ID::PRIORITY_MASK);
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for (int orig_portid : wr_portid) {
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bool has_prio = orig_portid < GetSize(orig_prio_mask) && orig_prio_mask[orig_portid] == State::S1;
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port.priority_mask.push_back(has_prio);
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}
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}
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}
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}
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if (index.inits.count(mem->name)) {
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std::vector<std::pair<int, MemInit>> inits;
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@ -592,37 +646,33 @@ namespace {
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for (auto &it : inits)
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res.inits.push_back(it.second);
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}
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for (int i = 0; i < GetSize(res.wr_ports); i++) {
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auto &port = res.wr_ports[i];
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port.priority_mask.resize(GetSize(res.wr_ports));
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for (int j = 0; j < i; j++) {
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auto &oport = res.wr_ports[j];
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if (port.clk_enable != oport.clk_enable)
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continue;
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if (port.clk_enable && port.clk != oport.clk)
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continue;
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if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
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continue;
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port.priority_mask[j] = true;
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}
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}
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for (int i = 0; i < GetSize(res.rd_ports); i++) {
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auto &port = res.rd_ports[i];
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port.transparency_mask.resize(GetSize(res.wr_ports));
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port.collision_x_mask.resize(GetSize(res.wr_ports));
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if (!rd_transparent[i])
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continue;
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if (!port.clk_enable)
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continue;
|
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for (int j = 0; j < GetSize(res.wr_ports); j++) {
|
||||
auto &wport = res.wr_ports[j];
|
||||
if (!wport.clk_enable)
|
||||
bool is_compat = port.cell->type == ID($memrd);
|
||||
if (is_compat) {
|
||||
port.transparency_mask.resize(GetSize(res.wr_ports));
|
||||
port.collision_x_mask.resize(GetSize(res.wr_ports));
|
||||
if (!rd_transparent[i])
|
||||
continue;
|
||||
if (port.clk != wport.clk)
|
||||
if (!port.clk_enable)
|
||||
continue;
|
||||
if (port.clk_polarity != wport.clk_polarity)
|
||||
continue;
|
||||
port.transparency_mask[j] = true;
|
||||
for (int j = 0; j < GetSize(res.wr_ports); j++) {
|
||||
auto &wport = res.wr_ports[j];
|
||||
if (!wport.clk_enable)
|
||||
continue;
|
||||
if (port.clk != wport.clk)
|
||||
continue;
|
||||
if (port.clk_polarity != wport.clk_polarity)
|
||||
continue;
|
||||
port.transparency_mask[j] = true;
|
||||
}
|
||||
} else {
|
||||
Const orig_trans_mask = port.cell->parameters.at(ID::TRANSPARENCY_MASK);
|
||||
Const orig_cx_mask = port.cell->parameters.at(ID::COLLISION_X_MASK);
|
||||
for (int orig_portid : wr_portid) {
|
||||
port.transparency_mask.push_back(orig_portid < GetSize(orig_trans_mask) && orig_trans_mask[orig_portid] == State::S1);
|
||||
port.collision_x_mask.push_back(orig_portid < GetSize(orig_cx_mask) && orig_cx_mask[orig_portid] == State::S1);
|
||||
}
|
||||
}
|
||||
}
|
||||
res.check();
|
||||
|
|
@ -635,6 +685,7 @@ namespace {
|
|||
cell->parameters.at(ID::OFFSET).as_int(),
|
||||
cell->parameters.at(ID::SIZE).as_int()
|
||||
);
|
||||
bool is_compat = cell->type == ID($mem);
|
||||
int abits = cell->parameters.at(ID::ABITS).as_int();
|
||||
res.packed = true;
|
||||
res.cell = cell;
|
||||
|
|
@ -662,65 +713,103 @@ namespace {
|
|||
}
|
||||
}
|
||||
}
|
||||
for (int i = 0; i < cell->parameters.at(ID::RD_PORTS).as_int(); i++) {
|
||||
int n_rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
|
||||
int n_wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
|
||||
Const rd_wide_continuation = is_compat ? Const(State::S0, n_rd_ports) : cell->parameters.at(ID::RD_WIDE_CONTINUATION);
|
||||
Const wr_wide_continuation = is_compat ? Const(State::S0, n_wr_ports) : cell->parameters.at(ID::WR_WIDE_CONTINUATION);
|
||||
for (int i = 0, ni; i < n_rd_ports; i = ni) {
|
||||
ni = i + 1;
|
||||
while (ni < n_rd_ports && rd_wide_continuation[ni] == State::S1)
|
||||
ni++;
|
||||
MemRd mrd;
|
||||
mrd.wide_log2 = 0;
|
||||
mrd.wide_log2 = ceil_log2(ni - i);
|
||||
log_assert(ni - i == (1 << mrd.wide_log2));
|
||||
mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool();
|
||||
mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool();
|
||||
mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1);
|
||||
mrd.en = cell->getPort(ID::RD_EN).extract(i, 1);
|
||||
mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits);
|
||||
mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, res.width);
|
||||
mrd.ce_over_srst = false;
|
||||
mrd.arst_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.srst_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.init_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.srst = State::S0;
|
||||
mrd.arst = State::S0;
|
||||
mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, (ni - i) * res.width);
|
||||
if (is_compat) {
|
||||
mrd.ce_over_srst = false;
|
||||
mrd.arst_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.srst_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.init_value = Const(State::Sx, res.width << mrd.wide_log2);
|
||||
mrd.arst = State::S0;
|
||||
mrd.srst = State::S0;
|
||||
} else {
|
||||
mrd.ce_over_srst = cell->parameters.at(ID::RD_CE_OVER_SRST).extract(i, 1).as_bool();
|
||||
mrd.arst_value = cell->parameters.at(ID::RD_ARST_VALUE).extract(i * res.width, (ni - i) * res.width);
|
||||
mrd.srst_value = cell->parameters.at(ID::RD_SRST_VALUE).extract(i * res.width, (ni - i) * res.width);
|
||||
mrd.init_value = cell->parameters.at(ID::RD_INIT_VALUE).extract(i * res.width, (ni - i) * res.width);
|
||||
mrd.arst = cell->getPort(ID::RD_ARST).extract(i, 1);
|
||||
mrd.srst = cell->getPort(ID::RD_SRST).extract(i, 1);
|
||||
}
|
||||
if (!is_compat) {
|
||||
Const transparency_mask = cell->parameters.at(ID::RD_TRANSPARENCY_MASK).extract(i * n_wr_ports, n_wr_ports);
|
||||
Const collision_x_mask = cell->parameters.at(ID::RD_COLLISION_X_MASK).extract(i * n_wr_ports, n_wr_ports);
|
||||
for (int j = 0; j < n_wr_ports; j++)
|
||||
if (wr_wide_continuation[j] != State::S1) {
|
||||
mrd.transparency_mask.push_back(transparency_mask[j] == State::S1);
|
||||
mrd.collision_x_mask.push_back(collision_x_mask[j] == State::S1);
|
||||
}
|
||||
}
|
||||
res.rd_ports.push_back(mrd);
|
||||
}
|
||||
for (int i = 0; i < cell->parameters.at(ID::WR_PORTS).as_int(); i++) {
|
||||
for (int i = 0, ni; i < n_wr_ports; i = ni) {
|
||||
ni = i + 1;
|
||||
while (ni < n_wr_ports && wr_wide_continuation[ni] == State::S1)
|
||||
ni++;
|
||||
MemWr mwr;
|
||||
mwr.wide_log2 = 0;
|
||||
mwr.wide_log2 = ceil_log2(ni - i);
|
||||
log_assert(ni - i == (1 << mwr.wide_log2));
|
||||
mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool();
|
||||
mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool();
|
||||
mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1);
|
||||
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, res.width);
|
||||
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
|
||||
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
|
||||
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, res.width);
|
||||
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
|
||||
if (!is_compat) {
|
||||
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
|
||||
for (int j = 0; j < n_wr_ports; j++)
|
||||
if (wr_wide_continuation[j] != State::S1)
|
||||
mwr.priority_mask.push_back(priority_mask[j] == State::S1);
|
||||
}
|
||||
res.wr_ports.push_back(mwr);
|
||||
}
|
||||
for (int i = 0; i < GetSize(res.wr_ports); i++) {
|
||||
auto &port = res.wr_ports[i];
|
||||
port.priority_mask.resize(GetSize(res.wr_ports));
|
||||
for (int j = 0; j < i; j++) {
|
||||
auto &oport = res.wr_ports[j];
|
||||
if (port.clk_enable != oport.clk_enable)
|
||||
continue;
|
||||
if (port.clk_enable && port.clk != oport.clk)
|
||||
continue;
|
||||
if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
|
||||
continue;
|
||||
port.priority_mask[j] = true;
|
||||
if (is_compat) {
|
||||
for (int i = 0; i < GetSize(res.wr_ports); i++) {
|
||||
auto &port = res.wr_ports[i];
|
||||
port.priority_mask.resize(GetSize(res.wr_ports));
|
||||
for (int j = 0; j < i; j++) {
|
||||
auto &oport = res.wr_ports[j];
|
||||
if (port.clk_enable != oport.clk_enable)
|
||||
continue;
|
||||
if (port.clk_enable && port.clk != oport.clk)
|
||||
continue;
|
||||
if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
|
||||
continue;
|
||||
port.priority_mask[j] = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
for (int i = 0; i < GetSize(res.rd_ports); i++) {
|
||||
auto &port = res.rd_ports[i];
|
||||
port.transparency_mask.resize(GetSize(res.wr_ports));
|
||||
port.collision_x_mask.resize(GetSize(res.wr_ports));
|
||||
if (!cell->parameters.at(ID::RD_TRANSPARENT).extract(i, 1).as_bool())
|
||||
continue;
|
||||
if (!port.clk_enable)
|
||||
continue;
|
||||
for (int j = 0; j < GetSize(res.wr_ports); j++) {
|
||||
auto &wport = res.wr_ports[j];
|
||||
if (!wport.clk_enable)
|
||||
for (int i = 0; i < GetSize(res.rd_ports); i++) {
|
||||
auto &port = res.rd_ports[i];
|
||||
port.transparency_mask.resize(GetSize(res.wr_ports));
|
||||
port.collision_x_mask.resize(GetSize(res.wr_ports));
|
||||
if (!cell->parameters.at(ID::RD_TRANSPARENT).extract(i, 1).as_bool())
|
||||
continue;
|
||||
if (port.clk != wport.clk)
|
||||
if (!port.clk_enable)
|
||||
continue;
|
||||
if (port.clk_polarity != wport.clk_polarity)
|
||||
continue;
|
||||
port.transparency_mask[j] = true;
|
||||
for (int j = 0; j < GetSize(res.wr_ports); j++) {
|
||||
auto &wport = res.wr_ports[j];
|
||||
if (!wport.clk_enable)
|
||||
continue;
|
||||
if (port.clk != wport.clk)
|
||||
continue;
|
||||
if (port.clk_polarity != wport.clk_polarity)
|
||||
continue;
|
||||
port.transparency_mask[j] = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
res.check();
|
||||
|
|
@ -736,7 +825,7 @@ std::vector<Mem> Mem::get_all_memories(Module *module) {
|
|||
res.push_back(mem_from_memory(module, it.second, index));
|
||||
}
|
||||
for (auto cell: module->cells()) {
|
||||
if (cell->type == ID($mem))
|
||||
if (cell->type.in(ID($mem), ID($mem_v2)))
|
||||
res.push_back(mem_from_cell(cell));
|
||||
}
|
||||
return res;
|
||||
|
|
@ -750,7 +839,7 @@ std::vector<Mem> Mem::get_selected_memories(Module *module) {
|
|||
res.push_back(mem_from_memory(module, it.second, index));
|
||||
}
|
||||
for (auto cell: module->selected_cells()) {
|
||||
if (cell->type == ID($mem))
|
||||
if (cell->type.in(ID($mem), ID($mem_v2)))
|
||||
res.push_back(mem_from_cell(cell));
|
||||
}
|
||||
return res;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue