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Merge remote-tracking branch 'origin/master' into xc7dsp

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This commit is contained in:
Eddie Hung 2019-09-18 12:23:22 -07:00
commit fd3b033903
18 changed files with 19482 additions and 978 deletions
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4
passes/opt/opt_expr.cc
View file

@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (b.is_fully_const()) {
if (b.is_fully_undef()) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
} else
if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));

19
passes/techmap/alumacc.cc
View file

@ -48,14 +48,25 @@ struct AlumaccWorker
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
if (GetSize(cached_lt) == 0)
cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
if (GetSize(cached_lt) == 0) {
if (is_signed) {
get_of();
get_sf();
cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
}
else
cached_lt = get_cf();
}
return cached_lt;
}
RTLIL::SigSpec get_gt() {
if (GetSize(cached_gt) == 0)
cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
if (GetSize(cached_gt) == 0) {
get_lt();
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
}
return cached_gt;
}