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Merge remote-tracking branch 'origin/master' into xc7dsp

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This commit is contained in:
Eddie Hung 2019-09-18 12:23:22 -07:00
commit fd3b033903
18 changed files with 19482 additions and 978 deletions
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11
frontends/ast/simplify.cc
View file

@ -2895,8 +2895,15 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map)
{
if (!index_var.empty() && type == AST_IDENTIFIER && str == index_var) {
current_scope[index_var]->children[0]->cloneInto(this);
return;
if (children.empty()) {
current_scope[index_var]->children[0]->cloneInto(this);
} else {
AstNode *p = new AstNode(AST_LOCALPARAM, current_scope[index_var]->children[0]->clone());
p->str = stringf("$genval$%d", autoidx++);
current_ast_mod->children.push_back(p);
str = p->str;
id2ast = p;
}
}
if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0)

10
frontends/verilog/const2ast.cc
View file

@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
digits.push_back(10 + *str - 'A');
else if (*str == 'x' || *str == 'X')
digits.push_back(0xf0);
else if (*str == 'z' || *str == 'Z')
else if (*str == 'z' || *str == 'Z' || *str == '?')
digits.push_back(0xf1);
else if (*str == '?')
digits.push_back(0xf2);
str++;
}
@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
else if (*it == 0xf1)
data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
else if (*it == 0xf2)
data.push_back(RTLIL::Sa);
else
data.push_back((*it & bitmask) ? State::S1 : State::S0);
}
@ -199,13 +195,13 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
if (str == endptr)
len_in_bits = -1;
// The "<bits>'s?[bodhBODH]<digits>" syntax
// The "<bits>'[sS]?[bodhBODH]<digits>" syntax
if (*endptr == '\'')
{
std::vector<RTLIL::State> data;
bool is_signed = false;
bool is_unsized = len_in_bits < 0;
if (*(endptr+1) == 's') {
if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
is_signed = true;
endptr++;
}

2
frontends/verilog/verilog_lexer.l
View file

@ -239,7 +239,7 @@ YOSYS_NAMESPACE_END
return TOK_CONSTVAL;
}
[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
[0-9]*[ \t]*\'[sS]?[bodhBODH]?[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONSTVAL;
}