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Merge branch 'main' into splitnetlist

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This commit is contained in:
Alain Dargelas 2024-10-21 15:49:23 -07:00
commit fcfa2fff31
6 changed files with 33 additions and 943 deletions
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8
Makefile
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@ -19,8 +19,7 @@ ENABLE_GHDL := 0
ENABLE_SLANG := 0
ENABLE_VERIFIC := 1
ENABLE_VERIFIC_SYSTEMVERILOG := 1
ENABLE_VERIFIC_GHDL := 1
ENABLE_VERIFIC_VHDL := 0
ENABLE_VERIFIC_VHDL := 1
ENABLE_VERIFIC_HIER_TREE := 1
ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
@ -524,9 +523,6 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
VERIFIC_COMPONENTS += verilog
endif
endif
ifeq ($(ENABLE_VERIFIC_GHDL),1)
CXXFLAGS += -DVERIFIC_GHDL_SUPPORT
endif
ifeq ($(ENABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
@ -701,8 +697,6 @@ OBJS += libs/minisat/SimpSolver.o
OBJS += libs/minisat/Solver.o
OBJS += libs/minisat/System.o
OBJS += libs/whereami/whereami.o
ifeq ($(ENABLE_ZLIB),1)
OBJS += libs/fst/fstapi.o
OBJS += libs/fst/fastlz.o