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write_verilog: Skip empty switches

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Krystine Sherwin 2026-01-07 13:09:49 +13:00
parent 0ab967b036
commit fcb8695261
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backends/verilog/verilog_backend.cc
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@ -2143,6 +2143,9 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw)
{ {
if (sw->cases.empty())
return true;
for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
if ((*it)->compare.size() == 0) { if ((*it)->compare.size() == 0) {
break; break;