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Consolidate csa tests.

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nella 2026-03-18 12:36:31 +01:00 • committed by nella
parent ab1c423692
commit fc9adae9a2
64 changed files with 641 additions and 704 deletions
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102
tests/csa_tree/csa_tree_sub_chains.ys Normal file
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@ -0,0 +1,102 @@
read_verilog <<EOT
module sub_3op(
input [7:0] a, b, c,
output [7:0] y
);
assign y = a - b + c;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-count 1 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module sub_mixed(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b - c + d;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-count 1 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module sub_all(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a - b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-count 3 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module sub_5op(
input [11:0] a, b, c, d, e,
output [11:0] y
);
assign y = a - b + c - d + e;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 4 t:$fa
select -assert-count 1 t:$add
select -assert-count 2 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module sub_signed(
input signed [7:0] a, b, c, d,
output signed [9:0] y
);
assign y = a + b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-count 2 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module sub_double_neg(
input [7:0] a, b, c,
output [7:0] y
);
wire [7:0] ab = a - b;
assign y = c - ab;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-count 1 t:$not
select -assert-none t:$sub
design -reset