mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-30 21:57:47 +00:00
Code Activity

Rename csa_tree to arith_tree.

Browse source
This commit is contained in:
nella 2026-04-08 12:14:02 +02:00 • committed by nella
parent c3c577f333
commit fc71719e6e
12 changed files with 90 additions and 90 deletions
Download patch file Download diff file Expand all files Collapse all files

77
tests/csa_tree/csa_tree_negative.ys
View file

@ -1,77 +0,0 @@
read_verilog <<EOT
module add2(
input [7:0] a, b,
output [7:0] y
);
assign y = a + b;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-none t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module add_fanout(
input [7:0] a, b, c,
output [7:0] mid, y
);
wire [7:0] ab = a + b;
assign mid = ab;
assign y = ab + c;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-none t:$fa
design -reset
read_verilog <<EOT
module sub2(
input [7:0] a, b,
output [7:0] y
);
assign y = a - b;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-none t:$fa
select -assert-count 1 t:$sub
design -reset
read_verilog <<EOT
module add_multi_const(
input [7:0] x,
output [7:0] y
);
assign y = 8'd1 + 8'd2 + 8'd3 + x;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-none t:$fa
select -assert-max 1 t:$add
design -reset
read_verilog <<EOT
module add_partial(
input [7:0] a, b, c, d, e,
output [7:0] mid, y
);
wire [7:0] ab = a + b;
assign mid = ab;
assign y = ab + c + d + e;
endmodule
EOT
hierarchy -auto-top
proc
csa_tree
select -assert-count 2 t:$fa
select -assert-count 2 t:$add
design -reset